mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
584 lines
14 KiB
C
584 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Andreas Heppel <aheppel@sysgo.de>
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*
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* (C) Copyright 2002, 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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/*
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* Old PCI routines
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*
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* Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
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* and change pci-uclass.c.
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*/
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#include <common.h>
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#include <command.h>
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#include <errno.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <pci.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define PCI_HOSE_OP(rw, size, type) \
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int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
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pci_dev_t dev, \
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int offset, type value) \
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{ \
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return hose->rw##_##size(hose, dev, offset, value); \
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}
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PCI_HOSE_OP(read, byte, u8 *)
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PCI_HOSE_OP(read, word, u16 *)
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PCI_HOSE_OP(read, dword, u32 *)
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PCI_HOSE_OP(write, byte, u8)
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PCI_HOSE_OP(write, word, u16)
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PCI_HOSE_OP(write, dword, u32)
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#define PCI_OP(rw, size, type, error_code) \
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int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
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{ \
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struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
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\
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if (!hose) \
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{ \
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error_code; \
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return -1; \
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} \
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\
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return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
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}
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PCI_OP(read, byte, u8 *, *value = 0xff)
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PCI_OP(read, word, u16 *, *value = 0xffff)
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PCI_OP(read, dword, u32 *, *value = 0xffffffff)
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PCI_OP(write, byte, u8, )
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PCI_OP(write, word, u16, )
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PCI_OP(write, dword, u32, )
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#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
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int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
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pci_dev_t dev, \
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int offset, type val) \
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{ \
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u32 val32; \
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\
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if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
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*val = -1; \
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return -1; \
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} \
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\
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*val = (val32 >> ((offset & (int)off_mask) * 8)); \
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\
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return 0; \
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}
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#define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
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int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
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pci_dev_t dev, \
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int offset, type val) \
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{ \
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u32 val32, mask, ldata, shift; \
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\
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if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
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return -1; \
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\
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shift = ((offset & (int)off_mask) * 8); \
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ldata = (((unsigned long)val) & val_mask) << shift; \
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mask = val_mask << shift; \
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val32 = (val32 & ~mask) | ldata; \
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\
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if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
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return -1; \
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\
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return 0; \
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}
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PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
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PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
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PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
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PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
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/*
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*
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*/
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static struct pci_controller* hose_head;
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struct pci_controller *pci_get_hose_head(void)
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{
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if (gd->hose)
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return gd->hose;
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return hose_head;
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}
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void pci_register_hose(struct pci_controller* hose)
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{
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struct pci_controller **phose = &hose_head;
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while(*phose)
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phose = &(*phose)->next;
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hose->next = NULL;
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*phose = hose;
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}
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struct pci_controller *pci_bus_to_hose(int bus)
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{
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struct pci_controller *hose;
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for (hose = pci_get_hose_head(); hose; hose = hose->next) {
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if (bus >= hose->first_busno && bus <= hose->last_busno)
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return hose;
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}
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printf("pci_bus_to_hose() failed\n");
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return NULL;
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}
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struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
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{
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struct pci_controller *hose;
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for (hose = pci_get_hose_head(); hose; hose = hose->next) {
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if (hose->cfg_addr == cfg_addr)
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return hose;
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}
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return NULL;
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}
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int pci_last_busno(void)
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{
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struct pci_controller *hose = pci_get_hose_head();
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if (!hose)
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return -1;
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while (hose->next)
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hose = hose->next;
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return hose->last_busno;
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}
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pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
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{
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struct pci_controller * hose;
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pci_dev_t bdf;
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int bus;
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for (hose = pci_get_hose_head(); hose; hose = hose->next) {
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for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
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bdf = pci_hose_find_devices(hose, bus, ids, &index);
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if (bdf != -1)
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return bdf;
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}
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}
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return -1;
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}
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int pci_hose_config_device(struct pci_controller *hose,
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pci_dev_t dev,
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unsigned long io,
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pci_addr_t mem,
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unsigned long command)
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{
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u32 bar_response;
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unsigned int old_command;
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pci_addr_t bar_value;
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pci_size_t bar_size;
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unsigned char pin;
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int bar, found_mem64;
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debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
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(u64)mem, command);
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pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
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for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
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pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
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pci_hose_read_config_dword(hose, dev, bar, &bar_response);
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if (!bar_response)
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continue;
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found_mem64 = 0;
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/* Check the BAR type and set our address mask */
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if (bar_response & PCI_BASE_ADDRESS_SPACE) {
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bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
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/* round up region base address to a multiple of size */
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io = ((io - 1) | (bar_size - 1)) + 1;
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bar_value = io;
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/* compute new region base address */
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io = io + bar_size;
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} else {
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if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
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PCI_BASE_ADDRESS_MEM_TYPE_64) {
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u32 bar_response_upper;
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u64 bar64;
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pci_hose_write_config_dword(hose, dev, bar + 4,
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0xffffffff);
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pci_hose_read_config_dword(hose, dev, bar + 4,
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&bar_response_upper);
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bar64 = ((u64)bar_response_upper << 32) | bar_response;
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bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
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found_mem64 = 1;
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} else {
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bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
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}
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/* round up region base address to multiple of size */
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mem = ((mem - 1) | (bar_size - 1)) + 1;
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bar_value = mem;
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/* compute new region base address */
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mem = mem + bar_size;
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}
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/* Write it out and update our limit */
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pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
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if (found_mem64) {
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bar += 4;
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#ifdef CONFIG_SYS_PCI_64BIT
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pci_hose_write_config_dword(hose, dev, bar,
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(u32)(bar_value >> 32));
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#else
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pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
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#endif
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}
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}
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/* Configure Cache Line Size Register */
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pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
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/* Configure Latency Timer */
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pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
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/* Disable interrupt line, if device says it wants to use interrupts */
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pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
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if (pin != 0) {
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pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
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PCI_INTERRUPT_LINE_DISABLE);
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}
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pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
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pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
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(old_command & 0xffff0000) | command);
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return 0;
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}
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/*
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*
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*/
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struct pci_config_table *pci_find_config(struct pci_controller *hose,
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unsigned short class,
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unsigned int vendor,
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unsigned int device,
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unsigned int bus,
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unsigned int dev,
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unsigned int func)
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{
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struct pci_config_table *table;
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for (table = hose->config_table; table && table->vendor; table++) {
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if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
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(table->device == PCI_ANY_ID || table->device == device) &&
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(table->class == PCI_ANY_ID || table->class == class) &&
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(table->bus == PCI_ANY_ID || table->bus == bus) &&
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(table->dev == PCI_ANY_ID || table->dev == dev) &&
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(table->func == PCI_ANY_ID || table->func == func)) {
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return table;
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}
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}
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return NULL;
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}
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void pci_cfgfunc_config_device(struct pci_controller *hose,
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pci_dev_t dev,
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struct pci_config_table *entry)
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{
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pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
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entry->priv[2]);
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}
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void pci_cfgfunc_do_nothing(struct pci_controller *hose,
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pci_dev_t dev, struct pci_config_table *entry)
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{
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}
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/*
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* HJF: Changed this to return int. I think this is required
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* to get the correct result when scanning bridges
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*/
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extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
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#ifdef CONFIG_PCI_SCAN_SHOW
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__weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
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{
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if (dev == PCI_BDF(hose->first_busno, 0, 0))
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return 0;
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return 1;
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}
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#endif /* CONFIG_PCI_SCAN_SHOW */
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int pci_hose_scan_bus(struct pci_controller *hose, int bus)
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{
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unsigned int sub_bus, found_multi = 0;
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unsigned short vendor, device, class;
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unsigned char header_type;
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#ifndef CONFIG_PCI_PNP
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struct pci_config_table *cfg;
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#endif
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pci_dev_t dev;
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#ifdef CONFIG_PCI_SCAN_SHOW
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static int indent = 0;
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#endif
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sub_bus = bus;
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for (dev = PCI_BDF(bus,0,0);
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dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
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PCI_MAX_PCI_FUNCTIONS - 1);
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dev += PCI_BDF(0, 0, 1)) {
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if (pci_skip_dev(hose, dev))
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continue;
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if (PCI_FUNC(dev) && !found_multi)
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continue;
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pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
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pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
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if (vendor == 0xffff || vendor == 0x0000)
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continue;
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if (!PCI_FUNC(dev))
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found_multi = header_type & 0x80;
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debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
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PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
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pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
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pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
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#ifdef CONFIG_PCI_FIXUP_DEV
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board_pci_fixup_dev(hose, dev, vendor, device, class);
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#endif
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#ifdef CONFIG_PCI_SCAN_SHOW
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indent++;
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/* Print leading space, including bus indentation */
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printf("%*c", indent + 1, ' ');
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if (pci_print_dev(hose, dev)) {
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printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
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PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
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vendor, device, pci_class_str(class >> 8));
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}
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#endif
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#ifdef CONFIG_PCI_PNP
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sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
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sub_bus);
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#else
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cfg = pci_find_config(hose, class, vendor, device,
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PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
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if (cfg) {
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cfg->config_device(hose, dev, cfg);
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sub_bus = max(sub_bus,
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(unsigned int)hose->current_busno);
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}
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#endif
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#ifdef CONFIG_PCI_SCAN_SHOW
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indent--;
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#endif
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if (hose->fixup_irq)
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hose->fixup_irq(hose, dev);
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}
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return sub_bus;
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}
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int pci_hose_scan(struct pci_controller *hose)
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{
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#if defined(CONFIG_PCI_BOOTDELAY)
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char *s;
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int i;
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if (!gd->pcidelay_done) {
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/* wait "pcidelay" ms (if defined)... */
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s = env_get("pcidelay");
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if (s) {
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int val = simple_strtoul(s, NULL, 10);
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for (i = 0; i < val; i++)
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udelay(1000);
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}
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gd->pcidelay_done = 1;
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}
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#endif /* CONFIG_PCI_BOOTDELAY */
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#ifdef CONFIG_PCI_SCAN_SHOW
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puts("PCI:\n");
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#endif
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/*
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* Start scan at current_busno.
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* PCIe will start scan at first_busno+1.
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*/
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/* For legacy support, ensure current >= first */
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if (hose->first_busno > hose->current_busno)
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hose->current_busno = hose->first_busno;
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#ifdef CONFIG_PCI_PNP
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pciauto_config_init(hose);
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#endif
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return pci_hose_scan_bus(hose, hose->current_busno);
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}
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void pci_init(void)
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{
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hose_head = NULL;
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/* allow env to disable pci init/enum */
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if (env_get("pcidisable") != NULL)
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return;
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/* now call board specific pci_init()... */
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pci_init_board();
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}
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/* Returns the address of the requested capability structure within the
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* device's PCI configuration space or 0 in case the device does not
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* support it.
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* */
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int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
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int cap)
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{
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int pos;
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u8 hdr_type;
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pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
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pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
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if (pos)
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pos = pci_find_cap(hose, dev, pos, cap);
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return pos;
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}
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/* Find the header pointer to the Capabilities*/
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int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
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u8 hdr_type)
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{
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u16 status;
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pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
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if (!(status & PCI_STATUS_CAP_LIST))
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return 0;
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switch (hdr_type) {
|
|
case PCI_HEADER_TYPE_NORMAL:
|
|
case PCI_HEADER_TYPE_BRIDGE:
|
|
return PCI_CAPABILITY_LIST;
|
|
case PCI_HEADER_TYPE_CARDBUS:
|
|
return PCI_CB_CAPABILITY_LIST;
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
|
|
{
|
|
int ttl = PCI_FIND_CAP_TTL;
|
|
u8 id;
|
|
u8 next_pos;
|
|
|
|
while (ttl--) {
|
|
pci_hose_read_config_byte(hose, dev, pos, &next_pos);
|
|
if (next_pos < CAP_START_POS)
|
|
break;
|
|
next_pos &= ~3;
|
|
pos = (int) next_pos;
|
|
pci_hose_read_config_byte(hose, dev,
|
|
pos + PCI_CAP_LIST_ID, &id);
|
|
if (id == 0xff)
|
|
break;
|
|
if (id == cap)
|
|
return pos;
|
|
pos += PCI_CAP_LIST_NEXT;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* pci_find_next_ext_capability - Find an extended capability
|
|
*
|
|
* Returns the address of the next matching extended capability structure
|
|
* within the device's PCI configuration space or 0 if the device does
|
|
* not support it. Some capabilities can occur several times, e.g., the
|
|
* vendor-specific capability, and this provides a way to find them all.
|
|
*/
|
|
int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev,
|
|
int start, int cap)
|
|
{
|
|
u32 header;
|
|
int ttl, pos = PCI_CFG_SPACE_SIZE;
|
|
|
|
/* minimum 8 bytes per capability */
|
|
ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
|
|
|
|
if (start)
|
|
pos = start;
|
|
|
|
pci_hose_read_config_dword(hose, dev, pos, &header);
|
|
if (header == 0xffffffff || header == 0)
|
|
return 0;
|
|
|
|
while (ttl-- > 0) {
|
|
if (PCI_EXT_CAP_ID(header) == cap && pos != start)
|
|
return pos;
|
|
|
|
pos = PCI_EXT_CAP_NEXT(header);
|
|
if (pos < PCI_CFG_SPACE_SIZE)
|
|
break;
|
|
|
|
pci_hose_read_config_dword(hose, dev, pos, &header);
|
|
if (header == 0xffffffff || header == 0)
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* pci_hose_find_ext_capability - Find an extended capability
|
|
*
|
|
* Returns the address of the requested extended capability structure
|
|
* within the device's PCI configuration space or 0 if the device does
|
|
* not support it.
|
|
*/
|
|
int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev,
|
|
int cap)
|
|
{
|
|
return pci_find_next_ext_capability(hose, dev, 0, cap);
|
|
}
|