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410c505cc1
Platforms with limited resources in SPL may enably OF_PLATDATA, this limits some of the library functions and cannot extract data from the device tree. This patch adds additional wrappers around these functions to only allow them when OF_CONTROL is enabled and OF_PLATDATA is not. Signed-off-by: Adam Ford <aford173@gmail.com>
931 lines
24 KiB
C
931 lines
24 KiB
C
/*
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* Basic I2C functions
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*
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* Copyright (c) 2004 Texas Instruments
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*
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* This package is free software; you can redistribute it and/or
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* modify it under the terms of the license found in the file
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* named COPYING that should have accompanied this file.
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*
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* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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*
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* Author: Jian Zhang jzhang@ti.com, Texas Instruments
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*
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* Copyright (c) 2003 Wolfgang Denk, wd@denx.de
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* Rewritten to fit into the current U-Boot framework
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*
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* Adapted for OMAP2420 I2C, r-woodruff2@ti.com
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*
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* Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
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* New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
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* (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
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* OMAPs and derivatives as well. The only anticipated exception would
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* be the OMAP2420, which shall require driver modification.
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* - Rewritten i2c_read to operate correctly with all types of chips
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* (old function could not read consistent data from some I2C slaves).
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* - Optimized i2c_write.
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* - New i2c_probe, performs write access vs read. The old probe could
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* hang the system under certain conditions (e.g. unconfigured pads).
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* - The read/write/probe functions try to identify unconfigured bus.
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* - Status functions now read irqstatus_raw as per TRM guidelines
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* (except for OMAP243X and OMAP34XX).
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* - Driver now supports up to I2C5 (OMAP5).
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*
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* Copyright (c) 2014 Hannes Schmelzer <oe5hpm@oevsv.at>, B&R
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* - Added support for set_speed
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*
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*/
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#include <common.h>
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#include <dm.h>
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#include <i2c.h>
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#include <asm/arch/i2c.h>
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#include <asm/io.h>
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#include "omap24xx_i2c.h"
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#define I2C_TIMEOUT 1000
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/* Absolutely safe for status update at 100 kHz I2C: */
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#define I2C_WAIT 200
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struct omap_i2c {
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struct udevice *clk;
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struct i2c *regs;
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unsigned int speed;
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int waitdelay;
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int clk_id;
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};
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static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
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{
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unsigned long internal_clk = 0, fclk;
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unsigned int prescaler;
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/*
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* This method is only called for Standard and Fast Mode speeds
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*
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* For some TI SoCs it is explicitly written in TRM (e,g, SPRUHZ6G,
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* page 5685, Table 24-7)
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* that the internal I2C clock (after prescaler) should be between
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* 7-12 MHz (at least for Fast Mode (FS)).
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*
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* Such approach is used in v4.9 Linux kernel in:
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* ./drivers/i2c/busses/i2c-omap.c (omap_i2c_init function).
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*/
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speed /= 1000; /* convert speed to kHz */
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if (speed > 100)
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internal_clk = 9600;
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else
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internal_clk = 4000;
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fclk = I2C_IP_CLK / 1000;
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prescaler = fclk / internal_clk;
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prescaler = prescaler - 1;
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if (speed > 100) {
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unsigned long scl;
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/* Fast mode */
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scl = internal_clk / speed;
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*pscl = scl - (scl / 3) - I2C_FASTSPEED_SCLL_TRIM;
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*psch = (scl / 3) - I2C_FASTSPEED_SCLH_TRIM;
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} else {
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/* Standard mode */
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*pscl = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLL_TRIM;
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*psch = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLH_TRIM;
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}
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debug("%s: speed [kHz]: %d psc: 0x%x sscl: 0x%x ssch: 0x%x\n",
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__func__, speed, prescaler, *pscl, *psch);
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if (*pscl <= 0 || *psch <= 0 || prescaler <= 0)
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return -EINVAL;
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return prescaler;
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}
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/*
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* Wait for the bus to be free by checking the Bus Busy (BB)
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* bit to become clear
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*/
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static int wait_for_bb(struct i2c *i2c_base, int waitdelay)
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{
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int timeout = I2C_TIMEOUT;
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u16 stat;
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writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
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#if defined(CONFIG_OMAP34XX)
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while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
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#else
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/* Read RAW status */
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while ((stat = readw(&i2c_base->irqstatus_raw) &
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I2C_STAT_BB) && timeout--) {
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#endif
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writew(stat, &i2c_base->stat);
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udelay(waitdelay);
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}
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if (timeout <= 0) {
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printf("Timed out in wait_for_bb: status=%04x\n",
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stat);
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return 1;
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}
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writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
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return 0;
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}
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/*
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* Wait for the I2C controller to complete current action
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* and update status
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*/
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static u16 wait_for_event(struct i2c *i2c_base, int waitdelay)
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{
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u16 status;
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int timeout = I2C_TIMEOUT;
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do {
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udelay(waitdelay);
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#if defined(CONFIG_OMAP34XX)
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status = readw(&i2c_base->stat);
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#else
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/* Read RAW status */
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status = readw(&i2c_base->irqstatus_raw);
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#endif
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} while (!(status &
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(I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
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I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
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I2C_STAT_AL)) && timeout--);
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if (timeout <= 0) {
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printf("Timed out in wait_for_event: status=%04x\n",
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status);
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/*
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* If status is still 0 here, probably the bus pads have
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* not been configured for I2C, and/or pull-ups are missing.
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*/
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printf("Check if pads/pull-ups of bus are properly configured\n");
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writew(0xFFFF, &i2c_base->stat);
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status = 0;
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}
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return status;
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}
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static void flush_fifo(struct i2c *i2c_base)
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{
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u16 stat;
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/*
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* note: if you try and read data when its not there or ready
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* you get a bus error
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*/
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while (1) {
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stat = readw(&i2c_base->stat);
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if (stat == I2C_STAT_RRDY) {
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readb(&i2c_base->data);
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writew(I2C_STAT_RRDY, &i2c_base->stat);
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udelay(1000);
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} else
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break;
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}
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}
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static int __omap24_i2c_setspeed(struct i2c *i2c_base, uint speed,
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int *waitdelay)
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{
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int psc, fsscll = 0, fssclh = 0;
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int hsscll = 0, hssclh = 0;
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u32 scll = 0, sclh = 0;
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if (speed >= OMAP_I2C_HIGH_SPEED) {
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/* High speed */
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psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
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psc -= 1;
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if (psc < I2C_PSC_MIN) {
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printf("Error : I2C unsupported prescaler %d\n", psc);
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return -1;
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}
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/* For first phase of HS mode */
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fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
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fssclh = fsscll;
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fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
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fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
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if (((fsscll < 0) || (fssclh < 0)) ||
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((fsscll > 255) || (fssclh > 255))) {
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puts("Error : I2C initializing first phase clock\n");
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return -1;
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}
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/* For second phase of HS mode */
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hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
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hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
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hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
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if (((fsscll < 0) || (fssclh < 0)) ||
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((fsscll > 255) || (fssclh > 255))) {
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puts("Error : I2C initializing second phase clock\n");
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return -1;
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}
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scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
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sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
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} else {
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/* Standard and fast speed */
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psc = omap24_i2c_findpsc(&scll, &sclh, speed);
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if (0 > psc) {
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puts("Error : I2C initializing clock\n");
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return -1;
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}
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}
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*waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
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writew(0, &i2c_base->con);
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writew(psc, &i2c_base->psc);
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writew(scll, &i2c_base->scll);
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writew(sclh, &i2c_base->sclh);
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writew(I2C_CON_EN, &i2c_base->con);
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writew(0xFFFF, &i2c_base->stat); /* clear all pending status */
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return 0;
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}
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static void omap24_i2c_deblock(struct i2c *i2c_base)
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{
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int i;
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u16 systest;
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u16 orgsystest;
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/* set test mode ST_EN = 1 */
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orgsystest = readw(&i2c_base->systest);
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systest = orgsystest;
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/* enable testmode */
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systest |= I2C_SYSTEST_ST_EN;
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writew(systest, &i2c_base->systest);
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systest &= ~I2C_SYSTEST_TMODE_MASK;
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systest |= 3 << I2C_SYSTEST_TMODE_SHIFT;
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writew(systest, &i2c_base->systest);
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/* set SCL, SDA = 1 */
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systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
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writew(systest, &i2c_base->systest);
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udelay(10);
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/* toggle scl 9 clocks */
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for (i = 0; i < 9; i++) {
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/* SCL = 0 */
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systest &= ~I2C_SYSTEST_SCL_O;
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writew(systest, &i2c_base->systest);
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udelay(10);
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/* SCL = 1 */
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systest |= I2C_SYSTEST_SCL_O;
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writew(systest, &i2c_base->systest);
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udelay(10);
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}
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/* send stop */
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systest &= ~I2C_SYSTEST_SDA_O;
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writew(systest, &i2c_base->systest);
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udelay(10);
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systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
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writew(systest, &i2c_base->systest);
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udelay(10);
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/* restore original mode */
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writew(orgsystest, &i2c_base->systest);
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}
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static void __omap24_i2c_init(struct i2c *i2c_base, int speed, int slaveadd,
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int *waitdelay)
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{
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int timeout = I2C_TIMEOUT;
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int deblock = 1;
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retry:
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if (readw(&i2c_base->con) & I2C_CON_EN) {
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writew(0, &i2c_base->con);
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udelay(50000);
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}
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writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
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udelay(1000);
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writew(I2C_CON_EN, &i2c_base->con);
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while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
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if (timeout <= 0) {
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puts("ERROR: Timeout in soft-reset\n");
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return;
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}
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udelay(1000);
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}
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if (0 != __omap24_i2c_setspeed(i2c_base, speed, waitdelay)) {
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printf("ERROR: failed to setup I2C bus-speed!\n");
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return;
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}
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/* own address */
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writew(slaveadd, &i2c_base->oa);
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#if defined(CONFIG_OMAP34XX)
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/*
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* Have to enable interrupts for OMAP2/3, these IPs don't have
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* an 'irqstatus_raw' register and we shall have to poll 'stat'
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*/
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writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
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I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
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#endif
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udelay(1000);
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flush_fifo(i2c_base);
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writew(0xFFFF, &i2c_base->stat);
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/* Handle possible failed I2C state */
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if (wait_for_bb(i2c_base, *waitdelay))
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if (deblock == 1) {
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omap24_i2c_deblock(i2c_base);
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deblock = 0;
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goto retry;
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}
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}
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/*
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* i2c_probe: Use write access. Allows to identify addresses that are
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* write-only (like the config register of dual-port EEPROMs)
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*/
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static int __omap24_i2c_probe(struct i2c *i2c_base, int waitdelay, uchar chip)
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{
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u16 status;
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int res = 1; /* default = fail */
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if (chip == readw(&i2c_base->oa))
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return res;
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/* Wait until bus is free */
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if (wait_for_bb(i2c_base, waitdelay))
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return res;
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/* No data transfer, slave addr only */
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writew(chip, &i2c_base->sa);
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/* Stop bit needed here */
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writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
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I2C_CON_STP, &i2c_base->con);
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status = wait_for_event(i2c_base, waitdelay);
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if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
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/*
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* With current high-level command implementation, notifying
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* the user shall flood the console with 127 messages. If
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* silent exit is desired upon unconfigured bus, remove the
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* following 'if' section:
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*/
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if (status == I2C_STAT_XRDY)
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printf("i2c_probe: pads on bus probably not configured (status=0x%x)\n",
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status);
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goto pr_exit;
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}
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/* Check for ACK (!NAK) */
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if (!(status & I2C_STAT_NACK)) {
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res = 0; /* Device found */
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udelay(waitdelay);/* Required by AM335X in SPL */
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/* Abort transfer (force idle state) */
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writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
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udelay(1000);
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writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX |
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I2C_CON_STP, &i2c_base->con); /* STP */
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}
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pr_exit:
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flush_fifo(i2c_base);
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writew(0xFFFF, &i2c_base->stat);
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return res;
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}
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|
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/*
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* i2c_read: Function now uses a single I2C read transaction with bulk transfer
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* of the requested number of bytes (note that the 'i2c md' command
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* limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
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* defined in the board config header, this transaction shall be with
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* Repeated Start (Sr) between the address and data phases; otherwise
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* Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
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* The address (reg offset) may be 0, 1 or 2 bytes long.
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* Function now reads correctly from chips that return more than one
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* byte of data per addressed register (like TI temperature sensors),
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* or that do not need a register address at all (such as some clock
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* distributors).
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*/
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static int __omap24_i2c_read(struct i2c *i2c_base, int waitdelay, uchar chip,
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uint addr, int alen, uchar *buffer, int len)
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{
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int i2c_error = 0;
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u16 status;
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if (alen < 0) {
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puts("I2C read: addr len < 0\n");
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return 1;
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}
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if (len < 0) {
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puts("I2C read: data len < 0\n");
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return 1;
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}
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if (buffer == NULL) {
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puts("I2C read: NULL pointer passed\n");
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return 1;
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}
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if (alen > 2) {
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printf("I2C read: addr len %d not supported\n", alen);
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return 1;
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}
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if (addr + len > (1 << 16)) {
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puts("I2C read: address out of range\n");
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return 1;
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}
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|
|
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
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|
/*
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|
* EEPROM chips that implement "address overflow" are ones
|
|
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
|
|
* address and the extra bits end up in the "chip address"
|
|
* bit slots. This makes a 24WC08 (1Kbyte) chip look like
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* four 256 byte chips.
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|
*
|
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* Note that we consider the length of the address field to
|
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* still be one byte because the extra address bits are
|
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* hidden in the chip address.
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*/
|
|
if (alen > 0)
|
|
chip |= ((addr >> (alen * 8)) &
|
|
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
|
|
#endif
|
|
|
|
/* Wait until bus not busy */
|
|
if (wait_for_bb(i2c_base, waitdelay))
|
|
return 1;
|
|
|
|
/* Zero, one or two bytes reg address (offset) */
|
|
writew(alen, &i2c_base->cnt);
|
|
/* Set slave address */
|
|
writew(chip, &i2c_base->sa);
|
|
|
|
if (alen) {
|
|
/* Must write reg offset first */
|
|
#ifdef CONFIG_I2C_REPEATED_START
|
|
/* No stop bit, use Repeated Start (Sr) */
|
|
writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
|
|
I2C_CON_TRX, &i2c_base->con);
|
|
#else
|
|
/* Stop - Start (P-S) */
|
|
writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP |
|
|
I2C_CON_TRX, &i2c_base->con);
|
|
#endif
|
|
/* Send register offset */
|
|
while (1) {
|
|
status = wait_for_event(i2c_base, waitdelay);
|
|
/* Try to identify bus that is not padconf'd for I2C */
|
|
if (status == I2C_STAT_XRDY) {
|
|
i2c_error = 2;
|
|
printf("i2c_read (addr phase): pads on bus probably not configured (status=0x%x)\n",
|
|
status);
|
|
goto rd_exit;
|
|
}
|
|
if (status == 0 || (status & I2C_STAT_NACK)) {
|
|
i2c_error = 1;
|
|
printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
|
|
status);
|
|
goto rd_exit;
|
|
}
|
|
if (alen) {
|
|
if (status & I2C_STAT_XRDY) {
|
|
alen--;
|
|
/* Do we have to use byte access? */
|
|
writeb((addr >> (8 * alen)) & 0xff,
|
|
&i2c_base->data);
|
|
writew(I2C_STAT_XRDY, &i2c_base->stat);
|
|
}
|
|
}
|
|
if (status & I2C_STAT_ARDY) {
|
|
writew(I2C_STAT_ARDY, &i2c_base->stat);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
/* Set slave address */
|
|
writew(chip, &i2c_base->sa);
|
|
/* Read len bytes from slave */
|
|
writew(len, &i2c_base->cnt);
|
|
/* Need stop bit here */
|
|
writew(I2C_CON_EN | I2C_CON_MST |
|
|
I2C_CON_STT | I2C_CON_STP,
|
|
&i2c_base->con);
|
|
|
|
/* Receive data */
|
|
while (1) {
|
|
status = wait_for_event(i2c_base, waitdelay);
|
|
/*
|
|
* Try to identify bus that is not padconf'd for I2C. This
|
|
* state could be left over from previous transactions if
|
|
* the address phase is skipped due to alen=0.
|
|
*/
|
|
if (status == I2C_STAT_XRDY) {
|
|
i2c_error = 2;
|
|
printf("i2c_read (data phase): pads on bus probably not configured (status=0x%x)\n",
|
|
status);
|
|
goto rd_exit;
|
|
}
|
|
if (status == 0 || (status & I2C_STAT_NACK)) {
|
|
i2c_error = 1;
|
|
goto rd_exit;
|
|
}
|
|
if (status & I2C_STAT_RRDY) {
|
|
*buffer++ = readb(&i2c_base->data);
|
|
writew(I2C_STAT_RRDY, &i2c_base->stat);
|
|
}
|
|
if (status & I2C_STAT_ARDY) {
|
|
writew(I2C_STAT_ARDY, &i2c_base->stat);
|
|
break;
|
|
}
|
|
}
|
|
|
|
rd_exit:
|
|
flush_fifo(i2c_base);
|
|
writew(0xFFFF, &i2c_base->stat);
|
|
return i2c_error;
|
|
}
|
|
|
|
/* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
|
|
static int __omap24_i2c_write(struct i2c *i2c_base, int waitdelay, uchar chip,
|
|
uint addr, int alen, uchar *buffer, int len)
|
|
{
|
|
int i;
|
|
u16 status;
|
|
int i2c_error = 0;
|
|
int timeout = I2C_TIMEOUT;
|
|
|
|
if (alen < 0) {
|
|
puts("I2C write: addr len < 0\n");
|
|
return 1;
|
|
}
|
|
|
|
if (len < 0) {
|
|
puts("I2C write: data len < 0\n");
|
|
return 1;
|
|
}
|
|
|
|
if (buffer == NULL) {
|
|
puts("I2C write: NULL pointer passed\n");
|
|
return 1;
|
|
}
|
|
|
|
if (alen > 2) {
|
|
printf("I2C write: addr len %d not supported\n", alen);
|
|
return 1;
|
|
}
|
|
|
|
if (addr + len > (1 << 16)) {
|
|
printf("I2C write: address 0x%x + 0x%x out of range\n",
|
|
addr, len);
|
|
return 1;
|
|
}
|
|
|
|
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
|
|
/*
|
|
* EEPROM chips that implement "address overflow" are ones
|
|
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
|
|
* address and the extra bits end up in the "chip address"
|
|
* bit slots. This makes a 24WC08 (1Kbyte) chip look like
|
|
* four 256 byte chips.
|
|
*
|
|
* Note that we consider the length of the address field to
|
|
* still be one byte because the extra address bits are
|
|
* hidden in the chip address.
|
|
*/
|
|
if (alen > 0)
|
|
chip |= ((addr >> (alen * 8)) &
|
|
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
|
|
#endif
|
|
|
|
/* Wait until bus not busy */
|
|
if (wait_for_bb(i2c_base, waitdelay))
|
|
return 1;
|
|
|
|
/* Start address phase - will write regoffset + len bytes data */
|
|
writew(alen + len, &i2c_base->cnt);
|
|
/* Set slave address */
|
|
writew(chip, &i2c_base->sa);
|
|
/* Stop bit needed here */
|
|
writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
|
|
I2C_CON_STP, &i2c_base->con);
|
|
|
|
while (alen) {
|
|
/* Must write reg offset (one or two bytes) */
|
|
status = wait_for_event(i2c_base, waitdelay);
|
|
/* Try to identify bus that is not padconf'd for I2C */
|
|
if (status == I2C_STAT_XRDY) {
|
|
i2c_error = 2;
|
|
printf("i2c_write: pads on bus probably not configured (status=0x%x)\n",
|
|
status);
|
|
goto wr_exit;
|
|
}
|
|
if (status == 0 || (status & I2C_STAT_NACK)) {
|
|
i2c_error = 1;
|
|
printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
|
|
status);
|
|
goto wr_exit;
|
|
}
|
|
if (status & I2C_STAT_XRDY) {
|
|
alen--;
|
|
writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data);
|
|
writew(I2C_STAT_XRDY, &i2c_base->stat);
|
|
} else {
|
|
i2c_error = 1;
|
|
printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",
|
|
status);
|
|
goto wr_exit;
|
|
}
|
|
}
|
|
/* Address phase is over, now write data */
|
|
for (i = 0; i < len; i++) {
|
|
status = wait_for_event(i2c_base, waitdelay);
|
|
if (status == 0 || (status & I2C_STAT_NACK)) {
|
|
i2c_error = 1;
|
|
printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
|
|
status);
|
|
goto wr_exit;
|
|
}
|
|
if (status & I2C_STAT_XRDY) {
|
|
writeb(buffer[i], &i2c_base->data);
|
|
writew(I2C_STAT_XRDY, &i2c_base->stat);
|
|
} else {
|
|
i2c_error = 1;
|
|
printf("i2c_write: bus not ready for data Tx (i=%d)\n",
|
|
i);
|
|
goto wr_exit;
|
|
}
|
|
}
|
|
/*
|
|
* poll ARDY bit for making sure that last byte really has been
|
|
* transferred on the bus.
|
|
*/
|
|
do {
|
|
status = wait_for_event(i2c_base, waitdelay);
|
|
} while (!(status & I2C_STAT_ARDY) && timeout--);
|
|
if (timeout <= 0)
|
|
printf("i2c_write: timed out writig last byte!\n");
|
|
|
|
wr_exit:
|
|
flush_fifo(i2c_base);
|
|
writew(0xFFFF, &i2c_base->stat);
|
|
return i2c_error;
|
|
}
|
|
|
|
#ifndef CONFIG_DM_I2C
|
|
/*
|
|
* The legacy I2C functions. These need to get removed once
|
|
* all users of this driver are converted to DM.
|
|
*/
|
|
static struct i2c *omap24_get_base(struct i2c_adapter *adap)
|
|
{
|
|
switch (adap->hwadapnr) {
|
|
case 0:
|
|
return (struct i2c *)I2C_BASE1;
|
|
break;
|
|
case 1:
|
|
return (struct i2c *)I2C_BASE2;
|
|
break;
|
|
#if (CONFIG_SYS_I2C_BUS_MAX > 2)
|
|
case 2:
|
|
return (struct i2c *)I2C_BASE3;
|
|
break;
|
|
#if (CONFIG_SYS_I2C_BUS_MAX > 3)
|
|
case 3:
|
|
return (struct i2c *)I2C_BASE4;
|
|
break;
|
|
#if (CONFIG_SYS_I2C_BUS_MAX > 4)
|
|
case 4:
|
|
return (struct i2c *)I2C_BASE5;
|
|
break;
|
|
#endif
|
|
#endif
|
|
#endif
|
|
default:
|
|
printf("wrong hwadapnr: %d\n", adap->hwadapnr);
|
|
break;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
|
|
static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
|
|
int alen, uchar *buffer, int len)
|
|
{
|
|
struct i2c *i2c_base = omap24_get_base(adap);
|
|
|
|
return __omap24_i2c_read(i2c_base, adap->waitdelay, chip, addr,
|
|
alen, buffer, len);
|
|
}
|
|
|
|
|
|
static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
|
|
int alen, uchar *buffer, int len)
|
|
{
|
|
struct i2c *i2c_base = omap24_get_base(adap);
|
|
|
|
return __omap24_i2c_write(i2c_base, adap->waitdelay, chip, addr,
|
|
alen, buffer, len);
|
|
}
|
|
|
|
static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
|
|
{
|
|
struct i2c *i2c_base = omap24_get_base(adap);
|
|
int ret;
|
|
|
|
ret = __omap24_i2c_setspeed(i2c_base, speed, &adap->waitdelay);
|
|
if (ret) {
|
|
pr_err("%s: set i2c speed failed\n", __func__);
|
|
return ret;
|
|
}
|
|
|
|
adap->speed = speed;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
|
|
{
|
|
struct i2c *i2c_base = omap24_get_base(adap);
|
|
|
|
return __omap24_i2c_init(i2c_base, speed, slaveadd, &adap->waitdelay);
|
|
}
|
|
|
|
static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
|
|
{
|
|
struct i2c *i2c_base = omap24_get_base(adap);
|
|
|
|
return __omap24_i2c_probe(i2c_base, adap->waitdelay, chip);
|
|
}
|
|
|
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
|
|
#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
|
|
#endif
|
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
|
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
|
|
#endif
|
|
|
|
U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
|
|
omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
|
|
CONFIG_SYS_OMAP24_I2C_SPEED,
|
|
CONFIG_SYS_OMAP24_I2C_SLAVE,
|
|
0)
|
|
U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
|
|
omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
|
|
CONFIG_SYS_OMAP24_I2C_SPEED1,
|
|
CONFIG_SYS_OMAP24_I2C_SLAVE1,
|
|
1)
|
|
#if (CONFIG_SYS_I2C_BUS_MAX > 2)
|
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
|
|
#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
|
|
#endif
|
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
|
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
|
|
#endif
|
|
|
|
U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
|
|
omap24_i2c_read, omap24_i2c_write, NULL,
|
|
CONFIG_SYS_OMAP24_I2C_SPEED2,
|
|
CONFIG_SYS_OMAP24_I2C_SLAVE2,
|
|
2)
|
|
#if (CONFIG_SYS_I2C_BUS_MAX > 3)
|
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
|
|
#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
|
|
#endif
|
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
|
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
|
|
#endif
|
|
|
|
U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
|
|
omap24_i2c_read, omap24_i2c_write, NULL,
|
|
CONFIG_SYS_OMAP24_I2C_SPEED3,
|
|
CONFIG_SYS_OMAP24_I2C_SLAVE3,
|
|
3)
|
|
#if (CONFIG_SYS_I2C_BUS_MAX > 4)
|
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
|
|
#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
|
|
#endif
|
|
#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
|
|
#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
|
|
#endif
|
|
|
|
U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
|
|
omap24_i2c_read, omap24_i2c_write, NULL,
|
|
CONFIG_SYS_OMAP24_I2C_SPEED4,
|
|
CONFIG_SYS_OMAP24_I2C_SLAVE4,
|
|
4)
|
|
#endif
|
|
#endif
|
|
#endif
|
|
|
|
#else /* CONFIG_DM_I2C */
|
|
|
|
static int omap_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
|
|
{
|
|
struct omap_i2c *priv = dev_get_priv(bus);
|
|
int ret;
|
|
|
|
debug("i2c_xfer: %d messages\n", nmsgs);
|
|
for (; nmsgs > 0; nmsgs--, msg++) {
|
|
debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
|
|
if (msg->flags & I2C_M_RD) {
|
|
ret = __omap24_i2c_read(priv->regs, priv->waitdelay,
|
|
msg->addr, 0, 0, msg->buf,
|
|
msg->len);
|
|
} else {
|
|
ret = __omap24_i2c_write(priv->regs, priv->waitdelay,
|
|
msg->addr, 0, 0, msg->buf,
|
|
msg->len);
|
|
}
|
|
if (ret) {
|
|
debug("i2c_write: error sending\n");
|
|
return -EREMOTEIO;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int omap_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
|
|
{
|
|
struct omap_i2c *priv = dev_get_priv(bus);
|
|
|
|
priv->speed = speed;
|
|
|
|
return __omap24_i2c_setspeed(priv->regs, speed, &priv->waitdelay);
|
|
}
|
|
|
|
static int omap_i2c_probe_chip(struct udevice *bus, uint chip_addr,
|
|
uint chip_flags)
|
|
{
|
|
struct omap_i2c *priv = dev_get_priv(bus);
|
|
|
|
return __omap24_i2c_probe(priv->regs, priv->waitdelay, chip_addr);
|
|
}
|
|
|
|
static int omap_i2c_probe(struct udevice *bus)
|
|
{
|
|
struct omap_i2c *priv = dev_get_priv(bus);
|
|
|
|
__omap24_i2c_init(priv->regs, priv->speed, 0, &priv->waitdelay);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
static int omap_i2c_ofdata_to_platdata(struct udevice *bus)
|
|
{
|
|
struct omap_i2c *priv = dev_get_priv(bus);
|
|
|
|
priv->regs = map_physmem(devfdt_get_addr(bus), sizeof(void *),
|
|
MAP_NOCACHE);
|
|
priv->speed = CONFIG_SYS_OMAP24_I2C_SPEED;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id omap_i2c_ids[] = {
|
|
{ .compatible = "ti,omap3-i2c" },
|
|
{ .compatible = "ti,omap4-i2c" },
|
|
{ }
|
|
};
|
|
#endif
|
|
|
|
static const struct dm_i2c_ops omap_i2c_ops = {
|
|
.xfer = omap_i2c_xfer,
|
|
.probe_chip = omap_i2c_probe_chip,
|
|
.set_bus_speed = omap_i2c_set_bus_speed,
|
|
};
|
|
|
|
U_BOOT_DRIVER(i2c_omap) = {
|
|
.name = "i2c_omap",
|
|
.id = UCLASS_I2C,
|
|
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
.of_match = omap_i2c_ids,
|
|
.ofdata_to_platdata = omap_i2c_ofdata_to_platdata,
|
|
#endif
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.probe = omap_i2c_probe,
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.priv_auto_alloc_size = sizeof(struct omap_i2c),
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.ops = &omap_i2c_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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#endif /* CONFIG_DM_I2C */
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