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9675d92027
As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
40 lines
667 B
Text
40 lines
667 B
Text
if TARGET_OPENPITON_RISCV64
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config SYS_BOARD
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default "riscv64"
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config SYS_VENDOR
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default "openpiton"
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config SYS_CPU
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default "generic"
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config SYS_CONFIG_NAME
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default "openpiton-riscv64"
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config TEXT_BASE
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default 0x81000000 if SPL
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default 0x80000000 if !RISCV_SMODE
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default 0x81000000 if RISCV_SMODE
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config SPL_TEXT_BASE
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default 0x82000000
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config SPL_OPENSBI_LOAD_ADDR
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default 0x80000000
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select ARCH_EARLY_INIT_R
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select SUPPORT_SPL
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imply CPU_RISCV
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imply RISCV_TIMER
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imply SPL_RISCV_ACLINT
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imply CMD_CPU
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imply SPL_CPU_SUPPORT
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imply SPL_SMP
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imply SPL_MMC
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imply SMP
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imply SPL_RISCV_MMODE
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endif
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