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LS1088A is compliant with the Layerscape Chassis Generation 3 with eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4 SDRAM memory controller with ECC, Data path acceleration architecture 2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs), QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> [YS: Revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
273 lines
11 KiB
Text
273 lines
11 KiB
Text
SoC overview
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1. LS1043A
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2. LS1088A
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3. LS2080A
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4. LS1012A
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5. LS1046A
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6. LS2088A
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7. LS2081A
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LS1043A
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---------
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The LS1043A integrated multicore processor combines four ARM Cortex-A53
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processor cores with datapath acceleration optimized for L2/3 packet
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processing, single pass security offload and robust traffic management
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and quality of service.
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The LS1043A SoC includes the following function and features:
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- Four 64-bit ARM Cortex-A53 CPUs
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- 1 MB unified L2 Cache
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- One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
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support
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- Data Path Acceleration Architecture (DPAA) incorporating acceleration the
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the following functions:
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- Packet parsing, classification, and distribution (FMan)
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- Queue management for scheduling, packet sequencing, and congestion
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management (QMan)
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- Hardware buffer management for buffer allocation and de-allocation (BMan)
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- Cryptography acceleration (SEC)
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- Ethernet interfaces by FMan
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- Up to 1 x XFI supporting 10G interface
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- Up to 1 x QSGMII
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- Up to 4 x SGMII supporting 1000Mbps
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- Up to 2 x SGMII supporting 2500Mbps
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- Up to 2 x RGMII supporting 1000Mbps
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- High-speed peripheral interfaces
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- Three PCIe 2.0 controllers, one supporting x4 operation
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- One serial ATA (SATA 3.0) controllers
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- Additional peripheral interfaces
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- Three high-speed USB 3.0 controllers with integrated PHY
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- Enhanced secure digital host controller (eSDXC/eMMC)
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- Quad Serial Peripheral Interface (QSPI) Controller
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- Serial peripheral interface (SPI) controller
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- Four I2C controllers
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- Two DUARTs
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- Integrated flash controller supporting NAND and NOR flash
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- QorIQ platform's trust architecture 2.1
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LS1088A
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--------
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The QorIQ LS1088A processor is built on the Layerscape
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architecture combining eight ARM A53 processor cores
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with advanced, high-performance datapath acceleration
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and networks, peripheral interfaces required for
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networking, wireless infrastructure, and general-purpose
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embedded applications.
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LS1088A is compliant with the Layerscape Chassis Generation 3.
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Features summary:
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- 8 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
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- Cores are in 2 cluster of 4-cores each
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- 1MB L2 - Cache per cluster
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- Cache coherent interconnect (CCI-400)
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- 1 64-bit DDR4 SDRAM memory controller with ECC
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- Data path acceleration architecture 2.0 (DPAA2)
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- 4-Lane 10GHz SerDes comprising of WRIOP
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- 4-Lane 10GHz SerDes comprising of PCI, SATA, uQE(TDM/HLDC/UART)
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- Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs
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- QSPI, SPI, IFC2.0 supporting NAND, NOR flash
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- 3 PCIe3.0 , 1 SATA3.0, 2 USB3.0, 1 SDXC, 2 DUARTs etc
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- 2 DUARTs
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- 4 I2C, GPIO
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- Thermal monitor unit(TMU)
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- 4 Flextimers and 1 generic timer
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- Support for hardware virtualization and partitioning enforcement
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- QorIQ platform's trust architecture 3.0
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- Service processor (SP) provides pre-boot initialization and secure-boot
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capabilities
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LS2080A
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--------
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The LS2080A integrated multicore processor combines eight ARM Cortex-A57
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processor cores with high-performance data path acceleration logic and network
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and peripheral bus interfaces required for networking, telecom/datacom,
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wireless infrastructure, and mil/aerospace applications.
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The LS2080A SoC includes the following function and features:
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- Eight 64-bit ARM Cortex-A57 CPUs
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- 1 MB platform cache with ECC
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- Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
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- One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
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the AIOP
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- Data path acceleration architecture (DPAA2) incorporating acceleration for
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the following functions:
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- Packet parsing, classification, and distribution (WRIOP)
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- Queue and Hardware buffer management for scheduling, packet sequencing, and
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congestion management, buffer allocation and de-allocation (QBMan)
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- Cryptography acceleration (SEC) at up to 10 Gbps
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- RegEx pattern matching acceleration (PME) at up to 10 Gbps
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- Decompression/compression acceleration (DCE) at up to 20 Gbps
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- Accelerated I/O processing (AIOP) at up to 20 Gbps
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- QDMA engine
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- 16 SerDes lanes at up to 10.3125 GHz
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- Ethernet interfaces
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- Up to eight 10 Gbps Ethernet MACs
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- Up to eight 1 / 2.5 Gbps Ethernet MACs
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- High-speed peripheral interfaces
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- Four PCIe 3.0 controllers, one supporting SR-IOV
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- Additional peripheral interfaces
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- Two serial ATA (SATA 3.0) controllers
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- Two high-speed USB 3.0 controllers with integrated PHY
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- Enhanced secure digital host controller (eSDXC/eMMC)
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- Serial peripheral interface (SPI) controller
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- Quad Serial Peripheral Interface (QSPI) Controller
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- Four I2C controllers
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- Two DUARTs
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- Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
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- Support for hardware virtualization and partitioning enforcement
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- QorIQ platform's trust architecture 3.0
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- Service processor (SP) provides pre-boot initialization and secure-boot
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capabilities
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LS1012A
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--------
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The LS1012A features an advanced 64-bit ARM v8 Cortex-
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A53 processor, with 32 KB of parity protected L1-I cache,
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32 KB of ECC protected L1-D cache, as well as 256 KB of
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ECC protected L2 cache.
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The LS1012A SoC includes the following function and features:
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- One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
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- ARM v8 cryptography extensions
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- One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
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16-/8-bit operation (no ECC support)
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- ARM core-link CCI-400 cache coherent interconnect
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- Packet Forwarding Engine (PFE)
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- Cryptography acceleration (SEC)
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- Ethernet interfaces supported by PFE:
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- One Configurable x3 SerDes:
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Two Serdes PLLs supported for usage by any SerDes data lane
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Support for up to 6 GBaud operation
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- High-speed peripheral interfaces:
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- One PCI Express Gen2 controller, supporting x1 operation
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- One serial ATA (SATA Gen 3.0) controller
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- One USB 3.0/2.0 controller with integrated PHY
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- One USB 2.0 controller with ULPI interface. .
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- Additional peripheral interfaces:
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- One quad serial peripheral interface (QuadSPI) controller
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- One serial peripheral interface (SPI) controller
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- Two enhanced secure digital host controllers
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- Two I2C controllers
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- One 16550 compliant DUART (two UART interfaces)
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- Two general purpose IOs (GPIO)
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- Two FlexTimers
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- Five synchronous audio interfaces (SAI)
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- Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
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- Single-source clocking solution enabling generation of core, platform,
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DDR, SerDes, and USB clocks from a single external crystal and internal
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crystaloscillator
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- Thermal monitor unit (TMU) with +/- 3C accuracy
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- Two WatchDog timers
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- ARM generic timer
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- QorIQ platform's trust architecture 2.1
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LS1046A
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--------
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The LS1046A integrated multicore processor combines four ARM Cortex-A72
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processor cores with datapath acceleration optimized for L2/3 packet
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processing, single pass security offload and robust traffic management
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and quality of service.
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The LS1046A SoC includes the following function and features:
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- Four 64-bit ARM Cortex-A72 CPUs
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- 2 MB unified L2 Cache
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- One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving
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support
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- Data Path Acceleration Architecture (DPAA) incorporating acceleration the
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the following functions:
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- Packet parsing, classification, and distribution (FMan)
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- Queue management for scheduling, packet sequencing, and congestion
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management (QMan)
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- Hardware buffer management for buffer allocation and de-allocation (BMan)
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- Cryptography acceleration (SEC)
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- Two Configurable x4 SerDes
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- Two PLLs per four-lane SerDes
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- Support for 10G operation
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- Ethernet interfaces by FMan
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- Up to 2 x XFI supporting 10G interface (MAC 9, 10)
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- Up to 1 x QSGMII (MAC 5, 6, 10, 1)
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- Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
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- Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
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- Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4)
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- High-speed peripheral interfaces
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- Three PCIe 3.0 controllers, one supporting x4 operation
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- One serial ATA (SATA 3.0) controllers
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- Additional peripheral interfaces
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- Three high-speed USB 3.0 controllers with integrated PHY
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- Enhanced secure digital host controller (eSDXC/eMMC)
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- Quad Serial Peripheral Interface (QSPI) Controller
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- Serial peripheral interface (SPI) controller
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- Four I2C controllers
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- Two DUARTs
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- Integrated flash controller (IFC) supporting NAND and NOR flash
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- QorIQ platform's trust architecture 2.1
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LS2088A
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--------
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The LS2088A integrated multicore processor combines eight ARM Cortex-A72
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processor cores with high-performance data path acceleration logic and network
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and peripheral bus interfaces required for networking, telecom/datacom,
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wireless infrastructure, and mil/aerospace applications.
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The LS2088A SoC includes the following function and features:
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- Eight 64-bit ARM Cortex-A72 CPUs
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- 1 MB platform cache with ECC
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- Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
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- One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
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the AIOP
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- Data path acceleration architecture (DPAA2) incorporating acceleration for
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the following functions:
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- Packet parsing, classification, and distribution (WRIOP)
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- Queue and Hardware buffer management for scheduling, packet sequencing, and
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congestion management, buffer allocation and de-allocation (QBMan)
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- Cryptography acceleration (SEC) at up to 10 Gbps
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- RegEx pattern matching acceleration (PME) at up to 10 Gbps
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- Decompression/compression acceleration (DCE) at up to 20 Gbps
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- Accelerated I/O processing (AIOP) at up to 20 Gbps
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- QDMA engine
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- 16 SerDes lanes at up to 10.3125 GHz
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- Ethernet interfaces
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- Up to eight 10 Gbps Ethernet MACs
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- Up to eight 1 / 2.5 Gbps Ethernet MACs
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- High-speed peripheral interfaces
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- Four PCIe 3.0 controllers, one supporting SR-IOV
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- Additional peripheral interfaces
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- Two serial ATA (SATA 3.0) controllers
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- Two high-speed USB 3.0 controllers with integrated PHY
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- Enhanced secure digital host controller (eSDXC/eMMC)
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- Serial peripheral interface (SPI) controller
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- Quad Serial Peripheral Interface (QSPI) Controller
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- Four I2C controllers
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- Two DUARTs
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- Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
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- Support for hardware virtualization and partitioning enforcement
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- QorIQ platform's trust architecture 3.0
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- Service processor (SP) provides pre-boot initialization and secure-boot
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capabilities
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LS2088A SoC has 3 more similar SoC personalities
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1)LS2048A, few difference w.r.t. LS2088A:
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a) Four 64-bit ARM v8 Cortex-A72 CPUs
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2)LS2084A, few difference w.r.t. LS2088A:
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a) No AIOP
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b) No 32-bit DDR3 SDRAM memory
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c) 5 * 1/10G + 5 *1G WRIOP
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d) No L2 switch
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3)LS2044A, few difference w.r.t. LS2084A:
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a) Four 64-bit ARM v8 Cortex-A72 CPUs
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LS2081A
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--------
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LS2081A is 40-pin derivative of LS2084A.
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So feature-wise it is same as LS2084A.
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Refer to LS2084A(LS2088A) section above for details.
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It has one more similar SoC personality
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1)LS2041A, few difference w.r.t. LS2081A:
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a) Four 64-bit ARM v8 Cortex-A72 CPUs
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