mirror of
https://github.com/AsahiLinux/u-boot
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f956fd0338
With BeagleBoard revision C some HW changes are introduced (e.g. PinMUX)
which might need different software handling. For this, GPIO pin 171 (GPIO
module 6, offset 11) can be used to check for board revision. If this pin
is low, we have a rev C board. Else it must be a revision Ax or Bx board.
To handle board differences you can call function beagle_get_revision().
E.g.:
if (beagle_get_revision()) {
/* do special revision C stuff here */
}
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
219 lines
5.9 KiB
C
219 lines
5.9 KiB
C
/*
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* (C) Copyright 2006-2008
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <x0khasim@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _OMAP3_H_
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#define _OMAP3_H_
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/* Stuff on L3 Interconnect */
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#define SMX_APE_BASE 0x68000000
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/* GPMC */
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#define OMAP34XX_GPMC_BASE 0x6E000000
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/* SMS */
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#define OMAP34XX_SMS_BASE 0x6C000000
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/* SDRC */
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#define OMAP34XX_SDRC_BASE 0x6D000000
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/*
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* L4 Peripherals - L4 Wakeup and L4 Core now
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*/
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#define OMAP34XX_CORE_L4_IO_BASE 0x48000000
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#define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000
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#define OMAP34XX_L4_PER 0x49000000
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#define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE
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/* CONTROL */
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#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000)
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/* UART */
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#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000)
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#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000)
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#define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000)
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/* General Purpose Timers */
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#define OMAP34XX_GPT1 0x48318000
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#define OMAP34XX_GPT2 0x49032000
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#define OMAP34XX_GPT3 0x49034000
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#define OMAP34XX_GPT4 0x49036000
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#define OMAP34XX_GPT5 0x49038000
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#define OMAP34XX_GPT6 0x4903A000
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#define OMAP34XX_GPT7 0x4903C000
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#define OMAP34XX_GPT8 0x4903E000
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#define OMAP34XX_GPT9 0x49040000
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#define OMAP34XX_GPT10 0x48086000
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#define OMAP34XX_GPT11 0x48088000
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#define OMAP34XX_GPT12 0x48304000
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/* WatchDog Timers (1 secure, 3 GP) */
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#define WD1_BASE 0x4830C000
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#define WD2_BASE 0x48314000
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#define WD3_BASE 0x49030000
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/* 32KTIMER */
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#define SYNC_32KTIMER_BASE 0x48320000
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#ifndef __ASSEMBLY__
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typedef struct s32ktimer {
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unsigned char res[0x10];
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unsigned int s32k_cr; /* 0x10 */
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} s32ktimer_t;
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#endif /* __ASSEMBLY__ */
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/* OMAP3 GPIO registers */
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#define OMAP34XX_GPIO1_BASE 0x48310000
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#define OMAP34XX_GPIO2_BASE 0x49050000
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#define OMAP34XX_GPIO3_BASE 0x49052000
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#define OMAP34XX_GPIO4_BASE 0x49054000
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#define OMAP34XX_GPIO5_BASE 0x49056000
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#define OMAP34XX_GPIO6_BASE 0x49058000
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#ifndef __ASSEMBLY__
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typedef struct gpio {
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unsigned char res1[0x34];
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unsigned int oe; /* 0x34 */
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unsigned int datain; /* 0x38 */
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unsigned char res2[0x54];
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unsigned int cleardataout; /* 0x90 */
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unsigned int setdataout; /* 0x94 */
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} gpio_t;
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#endif /* __ASSEMBLY__ */
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#define GPIO0 (0x1 << 0)
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#define GPIO1 (0x1 << 1)
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#define GPIO2 (0x1 << 2)
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#define GPIO3 (0x1 << 3)
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#define GPIO4 (0x1 << 4)
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#define GPIO5 (0x1 << 5)
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#define GPIO6 (0x1 << 6)
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#define GPIO7 (0x1 << 7)
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#define GPIO8 (0x1 << 8)
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#define GPIO9 (0x1 << 9)
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#define GPIO10 (0x1 << 10)
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#define GPIO11 (0x1 << 11)
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#define GPIO12 (0x1 << 12)
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#define GPIO13 (0x1 << 13)
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#define GPIO14 (0x1 << 14)
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#define GPIO15 (0x1 << 15)
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#define GPIO16 (0x1 << 16)
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#define GPIO17 (0x1 << 17)
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#define GPIO18 (0x1 << 18)
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#define GPIO19 (0x1 << 19)
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#define GPIO20 (0x1 << 20)
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#define GPIO21 (0x1 << 21)
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#define GPIO22 (0x1 << 22)
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#define GPIO23 (0x1 << 23)
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#define GPIO24 (0x1 << 24)
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#define GPIO25 (0x1 << 25)
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#define GPIO26 (0x1 << 26)
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#define GPIO27 (0x1 << 27)
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#define GPIO28 (0x1 << 28)
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#define GPIO29 (0x1 << 29)
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#define GPIO30 (0x1 << 30)
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#define GPIO31 (0x1 << 31)
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/* base address for indirect vectors (internal boot mode) */
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#define SRAM_OFFSET0 0x40000000
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#define SRAM_OFFSET1 0x00200000
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#define SRAM_OFFSET2 0x0000F800
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#define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \
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SRAM_OFFSET2)
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#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
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#define DEBUG_LED1 149 /* gpio */
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#define DEBUG_LED2 150 /* gpio */
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#define XDR_POP 5 /* package on package part */
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#define SDR_DISCRETE 4 /* 128M memory SDR module */
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#define DDR_STACKED 3 /* stacked part on 2422 */
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#define DDR_COMBO 2 /* combo part on cpu daughter card */
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#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */
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#define DDR_100 100 /* type found on most mem d-boards */
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#define DDR_111 111 /* some combo parts */
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#define DDR_133 133 /* most combo, some mem d-boards */
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#define DDR_165 165 /* future parts */
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#define CPU_3430 0x3430
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/*
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* 343x real hardware:
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* ES1 = rev 0
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*
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* 343x code defines:
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* ES1 = 0+1 = 1
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* ES1 = 1+1 = 1
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*/
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#define CPU_3430_ES1 1
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#define CPU_3430_ES2 2
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#define WIDTH_8BIT 0x0000
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#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
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/* SDP definitions according to FPGA Rev. Is this OK?? */
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#define SDP_3430_V1 0x1
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#define SDP_3430_V2 0x2
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/* EVM definitions */
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#define OMAP3EVM_V1 0x1
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#define OMAP3EVM_V2 0x2
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/* I2C power management companion definitions */
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#define PWRMGT_ADDR_ID1 0x48
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#define PWRMGT_ADDR_ID2 0x49
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#define PWRMGT_ADDR_ID3 0x4A
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#define PWRMGT_ADDR_ID4 0x4B
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/* I2C ID3 (slave3) register */
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#define LEDEN 0xEE
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#define LEDAON (0x1 << 0)
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#define LEDBON (0x1 << 1)
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#define LEDAPWM (0x1 << 4)
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#define LEDBPWM (0x1 << 5)
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/* I2C ID4 (slave4) register */
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#define VAUX2_DEV_GRP 0x76
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#define VAUX2_DEDICATED 0x79
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#define VAUX3_DEV_GRP 0x7A
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#define VAUX3_DEDICATED 0x7D
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#define VPLL2_DEV_GRP 0x8E
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#define VPLL2_DEDICATED 0x91
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#define VDAC_DEV_GRP 0x96
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#define VDAC_DEDICATED 0x99
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#define DEV_GRP_P1 0x20
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#define DEV_GRP_ALL 0xE0
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#define VAUX2_VSEL_28 0x09
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#define VAUX3_VSEL_28 0x03
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#define VPLL2_VSEL_18 0x05
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#define VDAC_VSEL_18 0x03
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#endif
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