mirror of
https://github.com/AsahiLinux/u-boot
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cfc67116a7
timer support interrupt controller support flash support ethernet support cache support board information support env support booting image support adding support for Xilinx ML401
90 lines
2.3 KiB
ArmAsm
90 lines
2.3 KiB
ArmAsm
/*
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* (C) Copyright 2007 Michal Simek
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* (C) Copyright 2004 Atmark Techno, Inc.
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*
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* Michal SIMEK <monstr@monstr.eu>
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* Yasushi SHOJI <yashi@atmark-techno.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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.text
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.global _start
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_start:
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mts rmsr, r0 /* disable cache */
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addi r1, r0, CFG_INIT_SP_OFFSET
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/* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
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addi r6, r0, 0xb000 /* hex b000 opcode imm */
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bslli r6, r6, 16 /* shift */
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swi r6, r0, 0x0 /* reset address */
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swi r6, r0, 0x8 /* user vector exception */
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swi r6, r0, 0x10 /* interrupt */
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swi r6, r0, 0x20 /* hardware exception */
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addi r6, r0, 0xb808 /* hew b808 opcode brai*/
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bslli r6, r6, 16
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swi r6, r0, 0x4 /* reset address */
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swi r6, r0, 0xC /* user vector exception */
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swi r6, r0, 0x14 /* interrupt */
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swi r6, r0, 0x24 /* hardware exception */
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#ifdef CFG_RESET_ADDRESS
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/* reset address */
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addik r6, r0, CFG_RESET_ADDRESS
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sw r6, r1, r0
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lhu r7, r1, r0
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shi r7, r0, 0x2
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shi r6, r0, 0x6
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#endif
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#ifdef CFG_USR_EXCEP
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/* user_vector_exception */
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addik r6, r0, _exception_handler
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sw r6, r1, r0
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lhu r7, r1, r0
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shi r7, r0, 0xa
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shi r6, r0, 0xe
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#endif
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#ifdef CFG_INTC_0
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/* interrupt_handler */
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addik r6, r0, _interrupt_handler
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sw r6, r1, r0
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lhu r7, r1, r0
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shi r7, r0, 0x12
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shi r6, r0, 0x16
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#endif
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/* hardware exception */
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addik r6, r0, _hw_exception_handler
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sw r6, r1, r0
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lhu r7, r1, r0
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shi r7, r0, 0x22
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shi r6, r0, 0x26
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/* enable instruction and data cache */
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mfs r12, rmsr
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ori r12, r12, 0xa0
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mts rmsr, r12
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/* jumping to board_init */
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brai board_init
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1: bri 1b
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