mirror of
https://github.com/AsahiLinux/u-boot
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124 lines
2.7 KiB
Text
124 lines
2.7 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* Copyright 2016 Toradex AG
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "imx7d.dtsi"
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/ {
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model = "Toradex Colibri iMX7S/D";
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compatible = "toradex,imx7-colibri", "fsl,imx7";
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chosen {
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stdout-path = &uart1;
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};
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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fsl,use-minimum-ecc;
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nand-on-flash-bbt;
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nand-ecc-mode = "hw";
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status = "okay";
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};
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&i2c1 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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sda-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
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scl-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
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status = "okay";
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rn5t567@33 {
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compatible = "ricoh,rn5t567";
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reg = <0x33>;
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};
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};
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&i2c4 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c4>;
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pinctrl-1 = <&pinctrl_i2c4_gpio>;
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sda-gpios = <&gpio7 9 GPIO_ACTIVE_LOW>;
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scl-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
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uart-has-rtscts;
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fsl,dte-mode;
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status = "okay";
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};
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&iomuxc {
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pinctrl_gpmi_nand: gpmi-nand-grp {
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fsl,pins = <
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MX7D_PAD_SD3_CLK__NAND_CLE 0x71
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MX7D_PAD_SD3_CMD__NAND_ALE 0x71
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MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71
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MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74
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MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71
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MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71
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MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71
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MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71
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MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71
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MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71
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MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71
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MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71
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MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71
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MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71
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>;
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};
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pinctrl_i2c4: i2c4-grp {
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fsl,pins = <
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MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f
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MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f
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>;
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};
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pinctrl_i2c4_gpio: i2c4-gpio-grp {
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fsl,pins = <
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MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f
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MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f
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>;
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};
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pinctrl_uart1: uart1-grp {
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fsl,pins = <
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MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79
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MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79
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MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79
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MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79
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>;
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};
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pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
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fsl,pins = <
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MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */
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MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */
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>;
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};
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};
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&iomuxc_lpsr {
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pinctrl_i2c1: i2c1-grp {
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fsl,pins = <
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MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f
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MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f
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>;
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};
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pinctrl_i2c1_gpio: i2c1-gpio-grp {
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fsl,pins = <
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MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f
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MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f
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>;
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};
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};
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