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82220526ac
RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers
share one pipe interface for each combo phy, here is the diagram
of the complex connection.
+----------------+
| | +------+
| USB3 OTG CTRL0 |---->| |
| | | | +------------+
+----------------+ | PIPE | | |
| MUX |---->| Combo PHY0 |
+----------------+ | | | |
| | | | +------------+
| SATA CTRL0 |---->| |
| | +------+
+----------------+
+----------------+
| | +------+
| USB3 HOST CTRL1|---->| |
| | | | +------------+
+----------------+ | PIPE | | |
| MUX |---->| Combo PHY1 |
+----------------+ | | | |
| |---->| | +------------+
| SATA CTRL1 | -->| |
| | | +------+
+----------------+ |
|
+----------------+ |
| | | +------+
| QSGMII CTRL |---->| |
| | | | +------------+
+----------------+ | PIPE | | |
| MUX |---->| Combo PHY2 |
+----------------+ | | | |
| |---->| | +------------+
| SATA CTRL2 | -->| |
| | | +------+
+----------------+ |
|
+----------------+ |
| | |
| PCIe2 1-Lane |---
| |
+----------------+
Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Co-developed-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
44 lines
1 KiB
Text
44 lines
1 KiB
Text
#
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# Phy drivers for Rockchip platforms
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#
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menu "Rockchip PHY driver"
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config PHY_ROCKCHIP_INNO_USB2
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bool "Rockchip INNO USB2PHY Driver"
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depends on ARCH_ROCKCHIP
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select PHY
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help
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Support for Rockchip USB2.0 PHY with Innosilicon IP block.
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config PHY_ROCKCHIP_NANENG_COMBOPHY
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bool "Support Rockchip NANENG combo PHY Driver"
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depends on ARCH_ROCKCHIP
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select PHY
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help
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Enable this to support the Rockchip NANENG combo PHY.
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config PHY_ROCKCHIP_PCIE
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bool "Rockchip PCIe PHY Driver"
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depends on ARCH_ROCKCHIP
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select PHY
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help
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Enable this to support the Rockchip PCIe PHY.
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config PHY_ROCKCHIP_SNPS_PCIE3
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bool "Rockchip Snps PCIe3 PHY Driver"
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depends on PHY && ARCH_ROCKCHIP
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help
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Support for Rockchip PCIe3 PHY with Synopsys IP block.
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It could support PCIe Gen3 single root complex, and could
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also be able splited into multiple combinations of lanes.
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config PHY_ROCKCHIP_TYPEC
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bool "Rockchip TYPEC PHY Driver"
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depends on ARCH_ROCKCHIP
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select PHY
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help
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Enable this to support the Rockchip USB TYPEC PHY.
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endmenu
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