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de8203653f
The ti816x SoC revision of the ethernet IP block is handled by the "davinci_emac" driver, rather than the "cpsw" driver as done by later members of the family. Enable the relevant plumbing. Signed-off-by: Sriramakrishnan <srk@ti.com> Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com> Signed-off-by: Tom Rini <trini@konsulko.com>
138 lines
3.6 KiB
C
138 lines
3.6 KiB
C
/*
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* evm.c
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*
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* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
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* Antoine Tenart, <atenart@adeneo-embedded.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spl.h>
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#include <netdev.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mux.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#if defined(CONFIG_NAND)
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gpmc_init();
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#endif
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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uint8_t mac_addr[6];
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uint32_t mac_hi, mac_lo;
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struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
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printf("<ethaddr> not set. Reading from E-fuse\n");
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/* try reading mac address from efuse */
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mac_lo = readl(&cdev->macid0l);
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mac_hi = readl(&cdev->macid0h);
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mac_addr[0] = mac_hi & 0xFF;
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mac_addr[1] = (mac_hi & 0xFF00) >> 8;
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mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
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mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
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mac_addr[4] = mac_lo & 0xFF;
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mac_addr[5] = (mac_lo & 0xFF00) >> 8;
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if (is_valid_ethaddr(mac_addr))
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eth_setenv_enetaddr("ethaddr", mac_addr);
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else
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printf("Unable to read MAC address. Set <ethaddr>\n");
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}
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return davinci_emac_initialize();
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}
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#ifdef CONFIG_SPL_BUILD
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static struct module_pin_mux mmc_pin_mux[] = {
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{ OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
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{ OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
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{ OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
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{ OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
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{ OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
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{ OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
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{ OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
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{ -1 },
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};
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void set_uart_mux_conf(void) {}
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void set_mux_conf_regs(void)
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{
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configure_module_pin_mux(mmc_pin_mux);
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}
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/*
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* EMIF Paramters. Refer the EMIF register documentation and the
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* memory datasheet for details. This is for 796 MHz.
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*/
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#define EMIF_TIM1 0x1779C9FE
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#define EMIF_TIM2 0x50608074
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#define EMIF_TIM3 0x009F857F
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#define EMIF_SDREF 0x10001841
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#define EMIF_SDCFG 0x62A73832
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#define EMIF_PHYCFG 0x00000110
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static const struct emif_regs ddr3_emif_regs = {
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.sdram_config = EMIF_SDCFG,
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.ref_ctrl = EMIF_SDREF,
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.sdram_tim1 = EMIF_TIM1,
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.sdram_tim2 = EMIF_TIM2,
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.sdram_tim3 = EMIF_TIM3,
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.emif_ddr_phy_ctlr_1 = EMIF_PHYCFG,
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};
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static const struct cmd_control ddr3_ctrl = {
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.cmd0csratio = 0x100,
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.cmd0iclkout = 0x001,
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.cmd1csratio = 0x100,
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.cmd1iclkout = 0x001,
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.cmd2csratio = 0x100,
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.cmd2iclkout = 0x001,
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};
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/* These values are obtained from the CCS app */
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#define RD_DQS_GATE (0x1B3)
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#define RD_DQS (0x35)
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#define WR_DQS (0x93)
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static struct ddr_data ddr3_data = {
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.datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)),
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.datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)),
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.datawiratio0 = ((0x20<<10) | 0x20<<0),
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.datagiratio0 = ((0x20<<10) | 0x20<<0),
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.datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
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.datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
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};
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static const struct dmm_lisa_map_regs evm_lisa_map_regs = {
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.dmm_lisa_map_0 = 0x00000000,
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.dmm_lisa_map_1 = 0x00000000,
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.dmm_lisa_map_2 = 0x80640300,
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.dmm_lisa_map_3 = 0xC0640320,
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};
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void sdram_init(void)
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{
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/*
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* Pass in our DDR3 config information and that we have 2 EMIFs to
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* configure.
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*/
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config_ddr(&ddr3_data, &ddr3_ctrl, &ddr3_emif_regs,
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&evm_lisa_map_regs, 2);
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}
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#endif /* CONFIG_SPL_BUILD */
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