Rick Chen cf6ee112d8 riscv: dts: move out AE350 L2 node from cpus node ... When L2 node exists inside cpus node, uclass_get_device can not parse L2 node successfully. So move it outside from cpus node. Also add tag-ram-ctl and data-ram-ctl attributes for v5l2 cache controller driver. This can adjust timing by requirement from dtb to improve performance. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>		2019-09-03 09:31:03 +08:00
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cpu	riscv: cache: Flush L2 cache before jump to linux	2019-09-03 09:31:03 +08:00
dts	riscv: dts: move out AE350 L2 node from cpus node	2019-09-03 09:31:03 +08:00
include/asm	riscv: add SPL support	2019-08-26 16:07:42 +08:00
lib	riscv: andes_plic: init plic by scanning each cpu node	2019-09-03 09:30:54 +08:00
config.mk	riscv: qemu: define standalone load address	2019-01-15 09:36:31 +08:00
Kconfig	riscv: add SPL support	2019-08-26 16:07:42 +08:00
Makefile	riscv: add Kconfig entries for the code model	2018-12-18 09:56:26 +08:00