mirror of
https://github.com/AsahiLinux/u-boot
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665624149a
Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
157 lines
3.7 KiB
C
157 lines
3.7 KiB
C
/*
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* (C) Copyright 2015
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* Kamil Lulko, <kamil.lulko@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <serial.h>
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#include <asm/arch/stm32.h>
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#include <dm/platform_data/serial_stm32.h>
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struct stm32_usart {
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u32 sr;
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u32 dr;
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u32 brr;
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u32 cr1;
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u32 cr2;
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u32 cr3;
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u32 gtpr;
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};
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#define USART_CR1_RE (1 << 2)
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#define USART_CR1_TE (1 << 3)
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#define USART_CR1_UE (1 << 13)
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#define USART_SR_FLAG_RXNE (1 << 5)
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#define USART_SR_FLAG_TXE (1 << 7)
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#define USART_BRR_F_MASK 0xF
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#define USART_BRR_M_SHIFT 4
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#define USART_BRR_M_MASK 0xFFF0
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DECLARE_GLOBAL_DATA_PTR;
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#define MAX_SERIAL_PORTS 4
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/*
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* RCC USART specific definitions
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*/
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#define RCC_ENR_USART1EN (1 << 4)
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#define RCC_ENR_USART2EN (1 << 17)
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#define RCC_ENR_USART3EN (1 << 18)
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#define RCC_ENR_USART6EN (1 << 5)
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/* Array used to figure out which RCC bit needs to be set */
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static const unsigned long usart_port_rcc_pairs[MAX_SERIAL_PORTS][2] = {
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{ STM32_USART1_BASE, RCC_ENR_USART1EN },
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{ STM32_USART2_BASE, RCC_ENR_USART2EN },
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{ STM32_USART3_BASE, RCC_ENR_USART3EN },
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{ STM32_USART6_BASE, RCC_ENR_USART6EN }
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};
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static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct stm32_serial_platdata *plat = dev->platdata;
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struct stm32_usart *const usart = plat->base;
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u32 clock, int_div, frac_div, tmp;
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if (((u32)usart & STM32_BUS_MASK) == STM32_APB1PERIPH_BASE)
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clock = clock_get(CLOCK_APB1);
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else if (((u32)usart & STM32_BUS_MASK) == STM32_APB2PERIPH_BASE)
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clock = clock_get(CLOCK_APB2);
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else
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return -EINVAL;
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int_div = (25 * clock) / (4 * baudrate);
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tmp = ((int_div / 100) << USART_BRR_M_SHIFT) & USART_BRR_M_MASK;
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frac_div = int_div - (100 * (tmp >> USART_BRR_M_SHIFT));
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tmp |= (((frac_div * 16) + 50) / 100) & USART_BRR_F_MASK;
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writel(tmp, &usart->brr);
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return 0;
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}
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static int stm32_serial_getc(struct udevice *dev)
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{
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struct stm32_serial_platdata *plat = dev->platdata;
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struct stm32_usart *const usart = plat->base;
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if ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0)
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return -EAGAIN;
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return readl(&usart->dr);
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}
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static int stm32_serial_putc(struct udevice *dev, const char c)
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{
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struct stm32_serial_platdata *plat = dev->platdata;
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struct stm32_usart *const usart = plat->base;
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if ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0)
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return -EAGAIN;
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writel(c, &usart->dr);
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return 0;
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}
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static int stm32_serial_pending(struct udevice *dev, bool input)
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{
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struct stm32_serial_platdata *plat = dev->platdata;
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struct stm32_usart *const usart = plat->base;
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if (input)
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return readl(&usart->sr) & USART_SR_FLAG_RXNE ? 1 : 0;
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else
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return readl(&usart->sr) & USART_SR_FLAG_TXE ? 0 : 1;
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}
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static int stm32_serial_probe(struct udevice *dev)
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{
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struct stm32_serial_platdata *plat = dev->platdata;
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struct stm32_usart *const usart = plat->base;
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int usart_port = -1;
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int i;
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for (i = 0; i < MAX_SERIAL_PORTS; i++) {
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if ((u32)usart == usart_port_rcc_pairs[i][0]) {
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usart_port = i;
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break;
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}
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}
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if (usart_port == -1)
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return -EINVAL;
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if (((u32)usart & STM32_BUS_MASK) == STM32_APB1PERIPH_BASE)
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setbits_le32(&STM32_RCC->apb1enr,
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usart_port_rcc_pairs[usart_port][1]);
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else if (((u32)usart & STM32_BUS_MASK) == STM32_APB2PERIPH_BASE)
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setbits_le32(&STM32_RCC->apb2enr,
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usart_port_rcc_pairs[usart_port][1]);
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else
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return -EINVAL;
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setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
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return 0;
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}
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static const struct dm_serial_ops stm32_serial_ops = {
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.putc = stm32_serial_putc,
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.pending = stm32_serial_pending,
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.getc = stm32_serial_getc,
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.setbrg = stm32_serial_setbrg,
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};
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U_BOOT_DRIVER(serial_stm32) = {
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.name = "serial_stm32",
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.id = UCLASS_SERIAL,
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.ops = &stm32_serial_ops,
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.probe = stm32_serial_probe,
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.flags = DM_FLAG_PRE_RELOC,
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};
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