mirror of
https://github.com/AsahiLinux/u-boot
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48b42616e9
- rewrite of the S3C24X0 register definitions stuff
- "driver" for the built-in S3C24X0 RTC
* Patches by Yuli Barcohen, 12 Jun 2003:
- Add MII support and Ethernet PHY initialization for MPC8260ADS board
- Fix incorrect SIUMCR initialisation caused by wrong Hard Reset
configuration word supplied by FPGA on some MPC8260ADS boards
* Patch by Pantelis Antoniou, 10 Jun 2003:
Unify status LED interface
97 lines
2.6 KiB
C
97 lines
2.6 KiB
C
/*
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* (C) Copyright 2001-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, d.mueller@elsoft.ch
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* This code should work for both the S3C2400 and the S3C2410
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* as they seem to have the same PLL and clock machinery inside.
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* The different address mapping is handled by the s3c24xx.h files below.
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*/
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#include <common.h>
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#if defined(CONFIG_S3C2400)
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#include <s3c2400.h>
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#elif defined(CONFIG_S3C2410)
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#include <s3c2410.h>
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#endif
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#define MPLL 0
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#define UPLL 1
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/* ------------------------------------------------------------------------- */
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/* NOTE: This describes the proper use of this file.
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*
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* CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
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*
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* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
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* the specified bus in HZ.
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*/
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/* ------------------------------------------------------------------------- */
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static ulong get_PLLCLK(int pllreg)
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{
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S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
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ulong r, m, p, s;
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if (pllreg == MPLL)
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r = clk_power->MPLLCON;
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else if (pllreg == UPLL)
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r = clk_power->UPLLCON;
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else
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hang();
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m = ((r & 0xFF000) >> 12) + 8;
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p = ((r & 0x003F0) >> 4) + 2;
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s = r & 0x3;
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return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
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}
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/* return FCLK frequency */
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ulong get_FCLK(void)
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{
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return(get_PLLCLK(MPLL));
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}
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/* return HCLK frequency */
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ulong get_HCLK(void)
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{
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S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
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return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
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}
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/* return PCLK frequency */
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ulong get_PCLK(void)
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{
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S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
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return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK());
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}
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/* return UCLK frequency */
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ulong get_UCLK(void)
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{
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return(get_PLLCLK(UPLL));
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}
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