mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-20 03:38:43 +00:00
cf3c142ee4
Added support for the following EDB93xx boards: EDB9301 EDB9302 EDB9302A EDB9307 EDB9307A EDB93012 EDB9315 EDB9315A Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
123 lines
3.1 KiB
C
123 lines
3.1 KiB
C
/*
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* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
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*
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* Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/io.h>
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#include "sdram_cfg.h"
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#include "early_udelay.h"
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#define PROGRAM_MODE_REG(bank) (*(volatile uint32_t *) \
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(SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL))
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#define PRECHARGE_BANK(bank) (*(volatile uint32_t *) \
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(SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank))
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static void force_precharge(void);
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static void setup_refresh_timer(void);
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static void program_mode_registers(void);
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void sdram_cfg(void)
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{
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struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
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writel(SDRAM_DEVCFG_VAL, &sdram->SDRAM_DEVCFG_REG);
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/* Issue continous NOP commands */
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writel(GLCONFIG_INIT | GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig);
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early_udelay(200);
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force_precharge();
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setup_refresh_timer();
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program_mode_registers();
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/* Select normal operation mode */
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writel(GLCONFIG_CKE, &sdram->glconfig);
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}
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static void force_precharge(void)
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{
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/*
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* Errata most EP93xx revisions say that PRECHARGE ALL isn't always
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* issued.
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*
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* Do a read from each bank to make sure they're precharged
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*/
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PRECHARGE_BANK(0);
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PRECHARGE_BANK(1);
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PRECHARGE_BANK(2);
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PRECHARGE_BANK(3);
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}
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static void setup_refresh_timer(void)
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{
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struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE;
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/* Load refresh timer with 10 to issue refresh every 10 cycles */
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writel(0x0a, &sdram->refrshtimr);
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/*
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* Wait at least 80 clock cycles to provide 8 refresh cycles
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* to all SDRAMs
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*/
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early_udelay(1);
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/*
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* Program refresh timer with normal value
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* We need 8192 refresh cycles every 64ms
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* at 15ns (HCLK >= 66MHz) per cycle:
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* 64ms / 8192 = 7.8125us
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* 7.8125us / 15ns = 520 (0x208)
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*/
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/*
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* TODO: redboot uses 0x1e0 for the slowest possible device
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* but i don't understand how this value is calculated
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*/
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writel(0x208, &sdram->refrshtimr);
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}
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static void program_mode_registers(void)
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{
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/*
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* The mode registers are programmed by performing a read from each
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* SDRAM bank. The value of the address that is read defines the value
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* that is written into the mode register
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*/
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PROGRAM_MODE_REG(0);
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#if (CONFIG_NR_DRAM_BANKS >= 2)
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PROGRAM_MODE_REG(1);
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#endif
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#if (CONFIG_NR_DRAM_BANKS >= 3)
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PROGRAM_MODE_REG(2);
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#endif
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#if (CONFIG_NR_DRAM_BANKS == 4)
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PROGRAM_MODE_REG(3);
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#endif
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}
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