Alim Akhtar 061091098a DMC: Exynos5: Enable update mode for DREX controller ... As per Exynos5800 UM ver 0.00 section 17.13.2.1 CONCONTROL register bit 3 [update_mode], Exynos5800 does not support the PHY initiated update. And it is recommanded to set this field to 1'b1 during initialization. This patch sets this bit. Applying MC-initiated mode makes DDL tracking ON, that helps in compensate MIF voltage variation. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>		2014-11-17 19:03:38 +09:00
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asm	DMC: Exynos5: Enable update mode for DREX controller	2014-11-17 19:03:38 +09:00
debug	arm: debug: replace license blocks with SPDX	2014-10-26 22:22:09 +01:00