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9839709ea3
This adds support for the Freescale COM Express P2020 board. This board is similar to the P1_P2_RDB, but has some extra (as well as missing) peripherals. Unlike all other mpc85xx boards, it uses a watchdog timeout to reset. Using the HRESET_REQ register does not work. This board has no NOR flash, and can only be booted via SD or SPI. This procedure is documented in Freescale Document Number AN3659 "Booting from On-Chip ROM (eSDHC or eSPI)." Some alternative documentation is provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated Processor Reference Manual" (section 4.5). Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
287 lines
6.3 KiB
C
287 lines
6.3 KiB
C
/*
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* Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <hwconfig.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/mpc85xx_gpio.h>
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#include <asm/fsl_serdes.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <fsl_mdio.h>
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#include <tsec.h>
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#include <vsc7385.h>
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#include <netdev.h>
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#include <mmc.h>
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#include <malloc.h>
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#include <i2c.h>
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#if defined(CONFIG_PCI)
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#include <asm/fsl_pci.h>
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#include <pci.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_PCI)
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void pci_init_board(void)
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{
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fsl_pcie_init_board(0);
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}
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void ft_pci_board_setup(void *blob)
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{
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FT_FSL_PCI_SETUP;
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}
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#endif
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#define BOARD_PERI_RST_SET (VSC7385_RST_SET | SLIC_RST_SET | \
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SGMII_PHY_RST_SET | PCIE_RST_SET | \
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RGMII_PHY_RST_SET)
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#define SYSCLK_MASK 0x00200000
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#define BOARDREV_MASK 0x10100000
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#define BOARDREV_B 0x10100000
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#define BOARDREV_C 0x00100000
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#define BOARDREV_D 0x00000000
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#define SYSCLK_66 66666666
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#define SYSCLK_50 50000000
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#define SYSCLK_100 100000000
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unsigned long get_board_sys_clk(ulong dummy)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
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ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
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switch (ddr_ratio) {
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case 0x0C:
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return SYSCLK_66;
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case 0x0A:
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case 0x08:
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return SYSCLK_100;
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default:
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puts("ERROR: unknown DDR ratio\n");
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return SYSCLK_100;
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}
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}
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unsigned long get_board_ddr_clk(ulong dummy)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
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ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
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switch (ddr_ratio) {
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case 0x0C:
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case 0x0A:
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return SYSCLK_66;
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case 0x08:
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return SYSCLK_100;
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default:
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puts("ERROR: unknown DDR ratio\n");
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return SYSCLK_100;
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}
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}
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#ifdef CONFIG_MMC
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int board_early_init_f(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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setbits_be32(&gur->pmuxcr,
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(MPC85xx_PMUXCR_SDHC_CD |
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MPC85xx_PMUXCR_SDHC_WP));
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/* All the device are enable except for SRIO12 */
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_SRIO);
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return 0;
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}
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#endif
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#define GPIO_DIR 0x0f3a0000
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#define GPIO_ODR 0x00000000
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#define GPIO_DAT 0x001a0000
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int checkboard(void)
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{
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ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xC00);
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/*
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* GPIO
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* 0 - 3: CarryBoard Input;
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* 4 - 7: CarryBoard Output;
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* 8 : Mux as SDHC_CD (card detection)
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* 9 : Mux as SDHC_WP
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* 10 : Clear Watchdog timer
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* 11 : LED Input
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* 12 : Output to 1
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* 13 : Open Drain
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* 14 : LED Output
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* 15 : Switch Input
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*
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* Set GPIOs 11, 12, 14 to 1.
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*/
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out_be32(&pgpio->gpodr, GPIO_ODR);
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mpc85xx_gpio_set(0xffffffff, GPIO_DIR, GPIO_DAT);
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puts("Board: Freescale COM Express P2020\n");
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return 0;
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}
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#define M41ST85W_I2C_BUS 1
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#define M41ST85W_I2C_ADDR 0x68
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#define M41ST85W_ERROR(fmt, args...) printf("ERROR: M41ST85W: " fmt, ##args)
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static void m41st85w_clear_bit(u8 reg, u8 mask, const char *name)
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{
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u8 data;
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if (i2c_read(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) {
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M41ST85W_ERROR("unable to read %s bit\n", name);
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return;
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}
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if (data & mask) {
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data &= ~mask;
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if (i2c_write(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) {
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M41ST85W_ERROR("unable to clear %s bit\n", name);
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return;
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}
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}
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}
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#define M41ST85W_REG_SEC2 0x01
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#define M41ST85W_REG_SEC2_ST 0x80
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#define M41ST85W_REG_ALHOUR 0x0c
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#define M41ST85W_REG_ALHOUR_HT 0x40
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/*
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* The P2020COME board has a STMicro M41ST85W RTC/watchdog
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* at i2c bus 1 address 0x68.
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*/
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static void start_rtc(void)
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{
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unsigned int bus = i2c_get_bus_num();
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if (i2c_set_bus_num(M41ST85W_I2C_BUS)) {
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M41ST85W_ERROR("unable to set i2c bus\n");
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goto out;
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}
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/* ensure ST (stop) and HT (halt update) bits are cleared */
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m41st85w_clear_bit(M41ST85W_REG_SEC2, M41ST85W_REG_SEC2_ST, "ST");
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m41st85w_clear_bit(M41ST85W_REG_ALHOUR, M41ST85W_REG_ALHOUR_HT, "HT");
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out:
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/* reset the i2c bus */
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i2c_set_bus_num(bus);
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}
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int board_early_init_r(void)
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{
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start_rtc();
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return 0;
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}
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#define M41ST85W_REG_WATCHDOG 0x09
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#define M41ST85W_REG_WATCHDOG_WDS 0x80
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#define M41ST85W_REG_WATCHDOG_BMB0 0x04
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void board_reset(void)
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{
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u8 data = M41ST85W_REG_WATCHDOG_WDS | M41ST85W_REG_WATCHDOG_BMB0;
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/* set the hardware watchdog timeout to 1/16 second, then hang */
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i2c_set_bus_num(M41ST85W_I2C_BUS);
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i2c_write(M41ST85W_I2C_ADDR, M41ST85W_REG_WATCHDOG, 1, &data, 1);
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while (1)
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/* hang */;
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}
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#ifdef CONFIG_TSEC_ENET
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int board_eth_init(bd_t *bis)
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{
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struct fsl_pq_mdio_info mdio_info;
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struct tsec_info_struct tsec_info[4];
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int num = 0;
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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num++;
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#endif
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#ifdef CONFIG_TSEC2
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SET_STD_TSEC_INFO(tsec_info[num], 2);
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num++;
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#endif
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#ifdef CONFIG_TSEC3
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SET_STD_TSEC_INFO(tsec_info[num], 3);
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if (is_serdes_configured(SGMII_TSEC3)) {
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puts("eTSEC3 is in sgmii mode.");
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tsec_info[num].flags |= TSEC_SGMII;
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}
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num++;
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#endif
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if (!num) {
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printf("No TSECs initialized\n");
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return 0;
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}
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mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
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mdio_info.name = DEFAULT_MII_NAME;
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fsl_pq_mdio_init(bis, &mdio_info);
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tsec_eth_init(bis, tsec_info, num);
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return pci_eth_init(bis);
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}
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#endif
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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#if defined(CONFIG_PCI)
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ft_pci_board_setup(blob);
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#endif
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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fdt_fixup_dr_usb(blob, bd);
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}
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#endif
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