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https://github.com/AsahiLinux/u-boot
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b7081d9197
This patch is required before the upcoming new enc28j60 driver using SPI framework patch can be applied: - Move legacy enc28j60.c to enc28j60_lpc2292.c. - Change Makefile and the two affected boards' definition files. Tested with ./MAKEALL ARM7 that both boards still compile. Signed-off-by: Reinhard Meyer<info@emk-elektronik.de> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
203 lines
6.3 KiB
C
203 lines
6.3 KiB
C
/*
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* (C) Copyright 2007
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Configuation settings for the SMN42 board from Siemens.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* If we are developing, we might want to start u-boot from ram
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* so we MUST NOT initialize critical regs like mem-timing ...
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*/
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#undef CONFIG_SKIP_LOWLEVEL_INIT
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#undef CONFIG_SKIP_RELOCATE_UBOOT
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
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#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */
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#define CONFIG_LPC2292
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#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
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#undef CONFIG_USE_IRQ /* don't need them anymore */
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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/*
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* Hardware drivers
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*/
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/*
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* select serial console configuration
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*/
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#define CONFIG_LPC2292_SERIAL
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#define CONFIG_SERIAL1 1 /* we use Serial line 1 */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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/* enable I2C and select the hardware/software driver */
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#undef CONFIG_HARD_I2C /* I2C with hardware support */
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#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
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/* this would be 0xAE if E0, E1 and E2 were pulled high */
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#define CONFIG_SYS_I2C_SLAVE 0xA0
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#define CONFIG_SYS_I2C_EEPROM_ADDR (0xA0 >> 1)
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit address */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes per write */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
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/* not used but required by devices.c */
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#define CONFIG_SYS_I2C_SPEED 10000
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#ifdef CONFIG_SOFT_I2C
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define SCL 0x00000004 /* P0.2 */
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#define SDA 0x00000008 /* P0.3 */
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#define I2C_READ ((GET32(IO0PIN) & SDA) ? 1 : 0)
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#define I2C_SDA(x) { if (x) PUT32(IO0SET, SDA); else PUT32(IO0CLR, SDA); }
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#define I2C_SCL(x) { if (x) PUT32(IO0SET, SCL); else PUT32(IO0CLR, SCL); }
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#define I2C_DELAY { udelay(100); }
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#define I2C_ACTIVE { unsigned int i2ctmp; \
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i2ctmp = GET32(IO0DIR); \
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i2ctmp |= SDA; \
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PUT32(IO0DIR, i2ctmp); }
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#define I2C_TRISTATE { unsigned int i2ctmp; \
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i2ctmp = GET32(IO0DIR); \
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i2ctmp &= ~SDA; \
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PUT32(IO0DIR, i2ctmp); }
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#endif /* CONFIG_SOFT_I2C */
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_MMC
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_PING
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#define CONFIG_DOS_PARTITION
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#define CONFIG_BOOTDELAY 5
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "SMN42 # " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x81800000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x83000000 /* 24 MB in SRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
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/* for uClinux img is here*/
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#define CONFIG_SYS_SYS_CLK_FREQ 58982400 /* Hz */
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#define CONFIG_SYS_HZ 2048 /* decrementer freq in Hz */
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/* valid baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*-----------------------------------------------------------------------
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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#endif
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SRAM */
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#define PHYS_SDRAM_1 0x81000000 /* SRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB SRAM */
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/* This is the external flash */
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#define PHYS_FLASH_1 0x80000000 /* Flash Bank #1 */
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#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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/*
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* The first entry in CONFIG_SYS_FLASH_BANKS_LIST is a dummy, but it must be present.
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*/
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#define CONFIG_SYS_FLASH_BANKS_LIST { 0, PHYS_FLASH_1 }
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#define CONFIG_SYS_FLASH_ADDR0 0x555
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#define CONFIG_SYS_FLASH_ADDR1 0x2AA
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#define CONFIG_SYS_FLASH_ERASE_TOUT 16384 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CONFIG_ENV_IS_IN_FLASH 1
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/* The Environment Sector is in the CPU-internal flash */
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#define CONFIG_SYS_FLASH_BASE 0
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#define CONFIG_ENV_OFFSET 0x3C000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
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#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_MMC 1
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/* we use this ethernet chip */
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#define CONFIG_ENC28J60_LPC2292
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#endif /* __CONFIG_H */
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