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https://github.com/AsahiLinux/u-boot
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e1a31034a6
Add support for SDHC adapter identification and configuration during board init. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
144 lines
4.1 KiB
C
144 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2011 Freescale Semiconductor
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* Copyright 2020 NXP
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* Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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*
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* This file provides support for the QIXIS of some Freescale reference boards.
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*/
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#ifndef __QIXIS_H_
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#define __QIXIS_H_
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struct qixis {
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u8 id; /* ID value uniquely identifying each QDS board type */
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u8 arch; /* Board version information */
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u8 scver; /* QIXIS Version Register */
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u8 model; /* Information of software programming model version */
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u8 tagdata;
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u8 ctl_sys;
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u8 aux; /* Auxiliary Register,0x06 */
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u8 clk_spd;
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u8 stat_dut;
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u8 stat_sys;
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u8 stat_alrm;
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u8 present;
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u8 present2; /* Presence Status Register 2,0x0c */
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u8 rcw_ctl;
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u8 ctl_led;
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u8 i2cblk;
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u8 rcfg_ctl; /* Reconfig Control Register,0x10 */
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u8 rcfg_st;
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u8 dcm_ad;
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u8 dcm_da;
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u8 dcmd;
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u8 dmsg;
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u8 gdc;
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u8 gdd; /* DCM Debug Data Register,0x17 */
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u8 dmack;
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u8 res1;
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u8 sdhc1;
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u8 sdhc2;
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u8 stat_pres3;
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u8 los_stat;
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u8 usb_ctl;
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u8 watch; /* Watchdog Register,0x1F */
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u8 pwr_ctl[2]; /* Power Control Register,0x20 */
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u8 res2[2];
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u8 pwr_stat[4]; /* Power Status Register,0x24 */
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u8 res3[8];
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u8 clk_spd2[2]; /* SYSCLK clock Speed Register,0x30 */
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u8 res4[2];
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u8 sclk[3]; /* Clock Configuration Registers,0x34 */
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u8 res5;
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u8 dclk[3];
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u8 res6;
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u8 clk_dspd[3];
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u8 res7;
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u8 rst_ctl; /* Reset Control Register,0x40 */
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u8 rst_stat; /* Reset Status Register */
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u8 rst_rsn; /* Reset Reason Register */
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u8 rst_frc[2]; /* Reset Force Registers,0x43 */
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u8 res8[11];
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u8 brdcfg[16]; /* Board Configuration Register,0x50 */
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u8 dutcfg[16];
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u8 rcw_ad[2]; /* RCW SRAM Address Registers,0x70 */
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u8 rcw_data;
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u8 res9[5];
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u8 post_ctl;
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u8 post_stat;
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u8 post_dat[2];
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u8 pi_d[4];
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u8 gpio_io[4];
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u8 gpio_dir[4];
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u8 res10[20];
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u8 rjtag_ctl;
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u8 rjtag_dat;
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u8 res11[2];
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u8 trig_src[4];
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u8 trig_dst[4];
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u8 trig_stat;
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u8 res12[3];
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u8 trig_ctr[4];
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u8 res13[16];
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u8 clk_freq[6]; /* Clock Measurement Registers */
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u8 res_c6[8];
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u8 clk_base[2]; /* Clock Frequency Base Reg */
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u8 res_d0[8];
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u8 cms[2]; /* Core Management Space Address Register, 0xD8 */
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u8 res_c0[6];
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u8 aux2[4]; /* Auxiliary Registers,0xE0 */
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u8 res14[10];
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u8 aux_ad;
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u8 aux_da;
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u8 res15[16];
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};
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u8 qixis_read(unsigned int reg);
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void qixis_write(unsigned int reg, u8 value);
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u16 qixis_read_minor(void);
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char *qixis_read_time(char *result);
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char *qixis_read_tag(char *buf);
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const char *byte_to_binary_mask(u8 val, u8 mask, char *buf);
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#ifdef CONFIG_SYS_I2C_FPGA_ADDR
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u8 qixis_read_i2c(unsigned int reg);
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void qixis_write_i2c(unsigned int reg, u8 value);
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#endif
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#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CONFIG_SYS_I2C_FPGA_ADDR)
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#define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg))
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#define QIXIS_WRITE(reg, value) \
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qixis_write_i2c(offsetof(struct qixis, reg), value)
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#else
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#define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg))
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#define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
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#endif
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#ifdef CONFIG_SYS_I2C_FPGA_ADDR
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#define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg))
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#define QIXIS_WRITE_I2C(reg, value) \
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qixis_write_i2c(offsetof(struct qixis, reg), value)
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#endif
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/* Use for SDHC adapter card type identification and operation */
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#define QIXIS_SDID_MASK 0x07
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#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC45 0x1 /* eMMC Card Rev4.5 */
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#define QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY 0x2 /* SD/MMC Legacy Card */
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#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC44 0x3 /* eMMC Card Rev4.4 */
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#define QIXIS_ESDHC_ADAPTER_TYPE_RSV 0x4 /* Reserved */
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#define QIXIS_ESDHC_ADAPTER_TYPE_MMC 0x5 /* MMC Card */
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#define QIXIS_ESDHC_ADAPTER_TYPE_SD 0x6 /* SD Card Rev2.0 3.0 */
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#define QIXIS_ESDHC_NO_ADAPTER 0x7 /* No Card is Present*/
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#define QIXIS_SDHC1_S1V3 0x80 /* SDHC1: SDHC1 3.3V power control */
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#define QIXIS_SDHC1_VS 0x30 /* BRDCFG11: route to SDHC1_VS */
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#define QIXIS_SDCLKIN 0x08
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#define QIXIS_SDCLKOUT 0x02
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#define QIXIS_DAT5_6_7 0X02
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#define QIXIS_DAT4 0X01
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#define QIXIS_EVDD_BY_SDHC_VS 0x0c
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#endif
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