mirror of
https://github.com/AsahiLinux/u-boot
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ce19d4ca7d
Pull the SPL code from porter.c into a separate file in preparation for the addition of system initialization code. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
55 lines
1.1 KiB
C
55 lines
1.1 KiB
C
/*
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* board/renesas/porter/porter_spl.c
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*
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* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <malloc.h>
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#include <dm/platform_data/serial_sh.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/rcar-mstp.h>
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#include <spl.h>
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#define TMU0_MSTP125 BIT(25)
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#define SD2CKCR 0xE615026C
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#define SD_97500KHZ 0x7
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void board_init_f(ulong dummy)
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{
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
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/*
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* SD0 clock is set to 97.5MHz by default.
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* Set SD2 to the 97.5MHz as well.
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*/
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writel(SD_97500KHZ, SD2CKCR);
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}
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void spl_board_init(void)
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{
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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}
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void board_boot_order(u32 *spl_boot_list)
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{
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/* Boot from SPI NOR with YMODEM UART fallback. */
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spl_boot_list[0] = BOOT_DEVICE_SPI;
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spl_boot_list[1] = BOOT_DEVICE_UART;
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spl_boot_list[2] = BOOT_DEVICE_NONE;
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}
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void reset_cpu(ulong addr)
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{
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}
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