mirror of
https://github.com/AsahiLinux/u-boot
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1e94b46f73
This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
395 lines
9.1 KiB
C
395 lines
9.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2007 Atmel Corporation
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <spi.h>
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#include <malloc.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91_spi.h>
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#if CONFIG_IS_ENABLED(DM_GPIO)
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#include <asm/gpio.h>
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#endif
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#include <linux/bitops.h>
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#include <linux/printk.h>
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/*
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* Register definitions for the Atmel AT32/AT91 SPI Controller
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*/
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/* Register offsets */
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#define ATMEL_SPI_CR 0x0000
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#define ATMEL_SPI_MR 0x0004
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#define ATMEL_SPI_RDR 0x0008
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#define ATMEL_SPI_TDR 0x000c
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#define ATMEL_SPI_SR 0x0010
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#define ATMEL_SPI_IER 0x0014
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#define ATMEL_SPI_IDR 0x0018
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#define ATMEL_SPI_IMR 0x001c
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#define ATMEL_SPI_CSR(x) (0x0030 + 4 * (x))
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#define ATMEL_SPI_VERSION 0x00fc
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/* Bits in CR */
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#define ATMEL_SPI_CR_SPIEN BIT(0)
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#define ATMEL_SPI_CR_SPIDIS BIT(1)
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#define ATMEL_SPI_CR_SWRST BIT(7)
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#define ATMEL_SPI_CR_LASTXFER BIT(24)
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/* Bits in MR */
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#define ATMEL_SPI_MR_MSTR BIT(0)
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#define ATMEL_SPI_MR_PS BIT(1)
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#define ATMEL_SPI_MR_PCSDEC BIT(2)
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#define ATMEL_SPI_MR_FDIV BIT(3)
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#define ATMEL_SPI_MR_MODFDIS BIT(4)
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#define ATMEL_SPI_MR_WDRBT BIT(5)
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#define ATMEL_SPI_MR_LLB BIT(7)
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#define ATMEL_SPI_MR_PCS(x) (((x) & 15) << 16)
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#define ATMEL_SPI_MR_DLYBCS(x) ((x) << 24)
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/* Bits in RDR */
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#define ATMEL_SPI_RDR_RD(x) (x)
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#define ATMEL_SPI_RDR_PCS(x) ((x) << 16)
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/* Bits in TDR */
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#define ATMEL_SPI_TDR_TD(x) (x)
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#define ATMEL_SPI_TDR_PCS(x) ((x) << 16)
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#define ATMEL_SPI_TDR_LASTXFER BIT(24)
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/* Bits in SR/IER/IDR/IMR */
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#define ATMEL_SPI_SR_RDRF BIT(0)
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#define ATMEL_SPI_SR_TDRE BIT(1)
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#define ATMEL_SPI_SR_MODF BIT(2)
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#define ATMEL_SPI_SR_OVRES BIT(3)
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#define ATMEL_SPI_SR_ENDRX BIT(4)
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#define ATMEL_SPI_SR_ENDTX BIT(5)
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#define ATMEL_SPI_SR_RXBUFF BIT(6)
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#define ATMEL_SPI_SR_TXBUFE BIT(7)
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#define ATMEL_SPI_SR_NSSR BIT(8)
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#define ATMEL_SPI_SR_TXEMPTY BIT(9)
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#define ATMEL_SPI_SR_SPIENS BIT(16)
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/* Bits in CSRx */
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#define ATMEL_SPI_CSRx_CPOL BIT(0)
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#define ATMEL_SPI_CSRx_NCPHA BIT(1)
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#define ATMEL_SPI_CSRx_CSAAT BIT(3)
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#define ATMEL_SPI_CSRx_BITS(x) ((x) << 4)
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#define ATMEL_SPI_CSRx_SCBR(x) ((x) << 8)
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#define ATMEL_SPI_CSRx_SCBR_MAX GENMASK(7, 0)
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#define ATMEL_SPI_CSRx_DLYBS(x) ((x) << 16)
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#define ATMEL_SPI_CSRx_DLYBCT(x) ((x) << 24)
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/* Bits in VERSION */
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#define ATMEL_SPI_VERSION_REV(x) ((x) & 0xfff)
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#define ATMEL_SPI_VERSION_MFN(x) ((x) << 16)
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/* Constants for CSRx:BITS */
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#define ATMEL_SPI_BITS_8 0
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#define ATMEL_SPI_BITS_9 1
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#define ATMEL_SPI_BITS_10 2
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#define ATMEL_SPI_BITS_11 3
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#define ATMEL_SPI_BITS_12 4
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#define ATMEL_SPI_BITS_13 5
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#define ATMEL_SPI_BITS_14 6
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#define ATMEL_SPI_BITS_15 7
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#define ATMEL_SPI_BITS_16 8
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#define MAX_CS_COUNT 4
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/* Register access macros */
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#define spi_readl(as, reg) \
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readl(as->regs + ATMEL_SPI_##reg)
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#define spi_writel(as, reg, value) \
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writel(value, as->regs + ATMEL_SPI_##reg)
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struct atmel_spi_plat {
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struct at91_spi *regs;
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};
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struct atmel_spi_priv {
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unsigned int freq; /* Default frequency */
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unsigned int mode;
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ulong bus_clk_rate;
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#if CONFIG_IS_ENABLED(DM_GPIO)
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struct gpio_desc cs_gpios[MAX_CS_COUNT];
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#endif
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};
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static int atmel_spi_claim_bus(struct udevice *dev)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct atmel_spi_plat *bus_plat = dev_get_plat(bus);
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struct atmel_spi_priv *priv = dev_get_priv(bus);
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struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
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struct at91_spi *reg_base = bus_plat->regs;
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u32 cs = slave_plat->cs;
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u32 freq = priv->freq;
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u32 scbr, csrx, mode;
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scbr = (priv->bus_clk_rate + freq - 1) / freq;
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if (scbr > ATMEL_SPI_CSRx_SCBR_MAX)
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return -EINVAL;
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if (scbr < 1)
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scbr = 1;
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csrx = ATMEL_SPI_CSRx_SCBR(scbr);
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csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8);
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if (!(priv->mode & SPI_CPHA))
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csrx |= ATMEL_SPI_CSRx_NCPHA;
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if (priv->mode & SPI_CPOL)
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csrx |= ATMEL_SPI_CSRx_CPOL;
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writel(csrx, ®_base->csr[cs]);
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mode = ATMEL_SPI_MR_MSTR |
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ATMEL_SPI_MR_MODFDIS |
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ATMEL_SPI_MR_WDRBT |
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ATMEL_SPI_MR_PCS(~(1 << cs));
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writel(mode, ®_base->mr);
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writel(ATMEL_SPI_CR_SPIEN, ®_base->cr);
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return 0;
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}
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static int atmel_spi_release_bus(struct udevice *dev)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct atmel_spi_plat *bus_plat = dev_get_plat(bus);
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writel(ATMEL_SPI_CR_SPIDIS, &bus_plat->regs->cr);
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return 0;
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}
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static void atmel_spi_cs_activate(struct udevice *dev)
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{
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#if CONFIG_IS_ENABLED(DM_GPIO)
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struct udevice *bus = dev_get_parent(dev);
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struct atmel_spi_priv *priv = dev_get_priv(bus);
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struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
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u32 cs = slave_plat->cs;
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if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
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return;
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dm_gpio_set_value(&priv->cs_gpios[cs], 0);
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#endif
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}
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static void atmel_spi_cs_deactivate(struct udevice *dev)
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{
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#if CONFIG_IS_ENABLED(DM_GPIO)
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struct udevice *bus = dev_get_parent(dev);
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struct atmel_spi_priv *priv = dev_get_priv(bus);
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struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
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u32 cs = slave_plat->cs;
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if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
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return;
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dm_gpio_set_value(&priv->cs_gpios[cs], 1);
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#endif
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}
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static int atmel_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct atmel_spi_plat *bus_plat = dev_get_plat(bus);
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struct at91_spi *reg_base = bus_plat->regs;
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u32 len_tx, len_rx, len;
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u32 status;
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const u8 *txp = dout;
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u8 *rxp = din;
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u8 value;
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if (bitlen == 0)
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goto out;
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/*
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* The controller can do non-multiple-of-8 bit
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* transfers, but this driver currently doesn't support it.
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*
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* It's also not clear how such transfers are supposed to be
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* represented as a stream of bytes...this is a limitation of
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* the current SPI interface.
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*/
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if (bitlen % 8) {
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/* Errors always terminate an ongoing transfer */
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flags |= SPI_XFER_END;
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goto out;
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}
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len = bitlen / 8;
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/*
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* The controller can do automatic CS control, but it is
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* somewhat quirky, and it doesn't really buy us much anyway
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* in the context of U-Boot.
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*/
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if (flags & SPI_XFER_BEGIN) {
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atmel_spi_cs_activate(dev);
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/*
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* sometimes the RDR is not empty when we get here,
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* in theory that should not happen, but it DOES happen.
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* Read it here to be on the safe side.
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* That also clears the OVRES flag. Required if the
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* following loop exits due to OVRES!
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*/
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readl(®_base->rdr);
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}
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for (len_tx = 0, len_rx = 0; len_rx < len; ) {
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status = readl(®_base->sr);
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if (status & ATMEL_SPI_SR_OVRES)
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return -1;
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if ((len_tx < len) && (status & ATMEL_SPI_SR_TDRE)) {
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if (txp)
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value = *txp++;
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else
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value = 0;
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writel(value, ®_base->tdr);
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len_tx++;
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}
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if (status & ATMEL_SPI_SR_RDRF) {
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value = readl(®_base->rdr);
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if (rxp)
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*rxp++ = value;
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len_rx++;
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}
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}
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out:
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if (flags & SPI_XFER_END) {
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/*
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* Wait until the transfer is completely done before
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* we deactivate CS.
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*/
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wait_for_bit_le32(®_base->sr,
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ATMEL_SPI_SR_TXEMPTY, true, 1000, false);
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atmel_spi_cs_deactivate(dev);
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}
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return 0;
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}
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static int atmel_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct atmel_spi_priv *priv = dev_get_priv(bus);
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priv->freq = speed;
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return 0;
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}
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static int atmel_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct atmel_spi_priv *priv = dev_get_priv(bus);
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priv->mode = mode;
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return 0;
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}
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static const struct dm_spi_ops atmel_spi_ops = {
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.claim_bus = atmel_spi_claim_bus,
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.release_bus = atmel_spi_release_bus,
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.xfer = atmel_spi_xfer,
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.set_speed = atmel_spi_set_speed,
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.set_mode = atmel_spi_set_mode,
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/*
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* cs_info is not needed, since we require all chip selects to be
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* in the device tree explicitly
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*/
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};
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static int atmel_spi_enable_clk(struct udevice *bus)
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{
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struct atmel_spi_priv *priv = dev_get_priv(bus);
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struct clk clk;
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ulong clk_rate;
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int ret;
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ret = clk_get_by_index(bus, 0, &clk);
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if (ret)
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return -EINVAL;
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ret = clk_enable(&clk);
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if (ret)
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return ret;
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clk_rate = clk_get_rate(&clk);
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if (!clk_rate)
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return -EINVAL;
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priv->bus_clk_rate = clk_rate;
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clk_free(&clk);
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return 0;
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}
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static int atmel_spi_probe(struct udevice *bus)
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{
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struct atmel_spi_plat *bus_plat = dev_get_plat(bus);
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int ret;
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ret = atmel_spi_enable_clk(bus);
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if (ret)
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return ret;
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bus_plat->regs = dev_read_addr_ptr(bus);
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#if CONFIG_IS_ENABLED(DM_GPIO)
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struct atmel_spi_priv *priv = dev_get_priv(bus);
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int i;
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ret = gpio_request_list_by_name(bus, "cs-gpios", priv->cs_gpios,
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ARRAY_SIZE(priv->cs_gpios), 0);
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if (ret < 0) {
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pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
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return ret;
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}
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for(i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
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if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
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continue;
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dm_gpio_set_dir_flags(&priv->cs_gpios[i],
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GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
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}
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#endif
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writel(ATMEL_SPI_CR_SWRST, &bus_plat->regs->cr);
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return 0;
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}
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static const struct udevice_id atmel_spi_ids[] = {
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{ .compatible = "atmel,at91rm9200-spi" },
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{ }
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};
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U_BOOT_DRIVER(atmel_spi) = {
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.name = "atmel_spi",
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.id = UCLASS_SPI,
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.of_match = atmel_spi_ids,
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.ops = &atmel_spi_ops,
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.plat_auto = sizeof(struct atmel_spi_plat),
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.priv_auto = sizeof(struct atmel_spi_priv),
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.probe = atmel_spi_probe,
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};
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