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3e01ed8e0f
Update R-Car Gen4 support in Gen3 clock driver. This patch renames the
V3U clock parts to Gen4 and extends them by new PLL2, PLL3, PLL4, PLL6
as well as SDSRC clock which use undocumented bits so far, and RPCSRC
clock which uses its own more capable divider table. The Gen4 module
standby and reset tables are also updated.
This patch makes use of union to alias Gen3 and more extensive Gen4
PLL tables, as the driver cannot ever be instantiated on hardware
that would identify itself as both Gen3 and Gen4.
The V3U clock driver is updated to match Gen4 clock driver behavior,
it is augmented with a more extensive PLL table and a valid MODEMR
register offset.
This supersedes "clk: renesas: Introduce R-Car Gen4 CPG driver"
from Hai Pham as the R-Car Gen3 and Gen4 clock core drivers are
extremely similar. That implementation was in turn based on Linux
commit 470e3f0d0b15 ("clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver")
by Yoshihiro Shimoda .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
167 lines
4.6 KiB
C
167 lines
4.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* R-Car Gen3 Clock Pulse Generator
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*
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* Copyright (C) 2015-2018 Glider bvba
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* Copyright (C) 2018 Renesas Electronics Corp.
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*
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*/
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#ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
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#define __CLK_RENESAS_RCAR_GEN3_CPG_H__
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enum rcar_gen3_clk_types {
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CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
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CLK_TYPE_GEN3_PLL0,
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CLK_TYPE_GEN3_PLL1,
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CLK_TYPE_GEN3_PLL2,
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CLK_TYPE_GEN3_PLL3,
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CLK_TYPE_GEN3_PLL4,
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CLK_TYPE_GEN3_SDH,
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CLK_TYPE_R8A77970_SD0H,
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CLK_TYPE_GEN3_SD,
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CLK_TYPE_R8A77970_SD0,
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CLK_TYPE_GEN3_R,
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CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
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CLK_TYPE_GEN3_Z,
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CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
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CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
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CLK_TYPE_GEN3_RPCSRC,
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CLK_TYPE_GEN3_D3_RPCSRC,
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CLK_TYPE_GEN3_E3_RPCSRC,
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CLK_TYPE_GEN3_RPC,
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CLK_TYPE_GEN3_RPCD2,
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CLK_TYPE_GEN4_MAIN,
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CLK_TYPE_GEN4_PLL1,
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CLK_TYPE_GEN4_PLL2,
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CLK_TYPE_GEN4_PLL2X_3X, /* R8A779A0 only */
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CLK_TYPE_GEN4_PLL3,
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CLK_TYPE_GEN4_PLL5,
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CLK_TYPE_GEN4_PLL4,
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CLK_TYPE_GEN4_PLL6,
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CLK_TYPE_GEN4_SDSRC,
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CLK_TYPE_GEN4_SDH,
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CLK_TYPE_GEN4_SD,
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CLK_TYPE_GEN4_MDSEL, /* Select parent/divider using mode pin */
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CLK_TYPE_GEN4_Z,
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CLK_TYPE_GEN4_OSC, /* OSC EXTAL predivider and fixed divider */
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CLK_TYPE_GEN4_RPCSRC,
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CLK_TYPE_GEN4_RPC,
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CLK_TYPE_GEN4_RPCD2,
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/* SoC specific definitions start here */
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CLK_TYPE_GEN3_SOC_BASE,
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};
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#define DEF_GEN3_SDH(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset)
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#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
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#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
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(_parent0) << 16 | (_parent1), \
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.div = (_div0) << 16 | (_div1), .offset = _md)
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#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
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_div_clean) \
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DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
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_parent_clean, _div_clean)
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#define DEF_GEN3_OSC(_name, _id, _parent, _div) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
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#define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
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(_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
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#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \
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DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
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#define DEF_FIXED_RPCSRC_D3(_name, _id, _parent0, _parent1) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_D3_RPCSRC, \
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(_parent0) << 16 | (_parent1), .div = 5)
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#define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \
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(_parent0) << 16 | (_parent1), .div = 8)
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#define DEF_GEN4_SDH(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
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#define DEF_GEN4_SD(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
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#define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \
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(_parent0) << 16 | (_parent1), \
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.div = (_div0) << 16 | (_div1), .offset = _md)
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#define DEF_GEN4_OSC(_name, _id, _parent, _div) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
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#define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \
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DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
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struct rcar_gen3_cpg_pll_config {
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u8 extal_div;
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u8 pll1_mult;
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u8 pll1_div;
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u8 pll3_mult;
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u8 pll3_div;
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u8 osc_prediv;
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};
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struct rcar_gen4_cpg_pll_config {
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u8 extal_div;
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u8 pll1_mult;
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u8 pll1_div;
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u8 pll2_mult;
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u8 pll2_div;
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u8 pll3_mult;
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u8 pll3_div;
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u8 pll4_mult;
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u8 pll4_div;
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u8 pll5_mult;
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u8 pll5_div;
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u8 pll6_mult;
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u8 pll6_div;
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u8 osc_prediv;
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};
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#define CPG_RST_MODEMR 0x060
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#define CPG_RST_MODEMR0 0x000
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#define CPG_SDCKCR_STPnHCK BIT(9)
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#define CPG_SDCKCR_STPnCK BIT(8)
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#define CPG_SDCKCR_SRCFC_MASK GENMASK(4, 2)
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#define CPG_SDCKCR_FC_MASK GENMASK(1, 0)
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/* V3M specifics */
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#define CPG_SDCKCR_SDHFC_MASK GENMASK(11, 8)
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#define CPG_SDCKCR_SD0FC_MASK GENMASK(7, 4)
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#define CPG_RPCCKCR 0x238
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#define CPG_RPCCKCR_DIV_POST_MASK GENMASK(4, 3)
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#define CPG_RPCCKCR_DIV_PRE_MASK GENMASK(2, 0)
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#define CPG_RCKCR 0x240
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struct gen3_clk_priv {
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void __iomem *base;
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struct cpg_mssr_info *info;
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struct clk clk_extal;
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struct clk clk_extalr;
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u32 cpg_mode;
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union {
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const struct rcar_gen3_cpg_pll_config *gen3_cpg_pll_config;
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const struct rcar_gen4_cpg_pll_config *gen4_cpg_pll_config;
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};
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};
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int gen3_cpg_bind(struct udevice *parent);
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extern const struct clk_ops gen3_clk_ops;
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#endif
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