mirror of
https://github.com/AsahiLinux/u-boot
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cd93d625fd
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
69 lines
1.6 KiB
C
69 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2017 Intel Corporation.
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*/
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#ifndef ASM_FAST_SPI_H
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#define ASM_FAST_SPI_H
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/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */
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#include <linux/bitops.h>
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struct fast_spi_regs {
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u32 bfp;
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u32 hsfsts_ctl;
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u32 faddr;
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u32 dlock;
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u32 fdata[0x10];
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u32 fracc;
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u32 freg[12];
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u32 fpr[5];
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u32 gpr0;
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u32 spare2;
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u32 sts_ctl;
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u16 preop;
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u16 optype;
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u8 opmenu[8];
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u32 spare3;
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u32 fdoc;
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u32 fdod;
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u32 spare4;
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u32 afc;
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u32 vscc[2];
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u32 ptinx;
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u32 ptdata;
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};
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check_member(fast_spi_regs, ptdata, 0xd0);
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/* Bit definitions for BFPREG (0x00) register */
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#define SPIBAR_BFPREG_PRB_MASK 0x7fff
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#define SPIBAR_BFPREG_PRL_SHIFT 16
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#define SPIBAR_BFPREG_PRL_MASK (0x7fff << SPIBAR_BFPREG_PRL_SHIFT)
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/* PCI configuration registers */
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#define SPIBAR_BIOS_CONTROL 0xdc
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#define SPIBAR_BIOS_CONTROL_WPD BIT(0)
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#define SPIBAR_BIOS_CONTROL_LOCK_ENABLE BIT(1)
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#define SPIBAR_BIOS_CONTROL_CACHE_DISABLE BIT(2)
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#define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE BIT(3)
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#define SPIBAR_BIOS_CONTROL_EISS BIT(5)
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#define SPIBAR_BIOS_CONTROL_BILD BIT(7)
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/**
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* fast_spi_get_bios_mmap() - Get memory map for SPI flash
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*
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* @pdev: PCI device to use (this is the Fast SPI device)
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* @map_basep: Returns base memory address for mapped SPI
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* @map_sizep: Returns size of mapped SPI
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* @offsetp: Returns start offset of SPI flash where the map works
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* correctly (offsets before this are not visible)
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* @return 0 (always)
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*/
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int fast_spi_get_bios_mmap(pci_dev_t pdev, ulong *map_basep, uint *map_sizep,
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uint *offsetp);
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int fast_spi_early_init(pci_dev_t pdev, ulong mmio_base);
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#endif /* ASM_FAST_SPI_H */
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