mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
118 lines
2.5 KiB
C
118 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Board functions for Sysam AMCORE (MCF5307 based) board
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*
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* (C) Copyright 2016 Angelo Dureghello <angelo@sysam.it>
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*
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* This file copies memory testdram() from sandburst/common/sb_common.c
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*/
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#include <common.h>
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#include <asm/immap.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <dm/platform_data/serial_coldfire.h>
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DECLARE_GLOBAL_DATA_PTR;
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void init_lcd(void)
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{
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/* setup for possible K0108 lcd connected on the parallel port */
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sim_t *sim = (sim_t *)(MMAP_SIM);
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out_be16(&sim->par, 0x300);
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gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
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out_be16(&gpio->paddr, 0xfcff);
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out_be16(&gpio->padat, 0x0c00);
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}
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int checkboard(void)
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{
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puts("Board: ");
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puts("AMCORE v.001(alpha)\n");
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init_lcd();
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return 0;
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}
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/*
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* in dram_init we are here executing from flash
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* case 1:
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* is with no ACR/flash cache enabled
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* nop = 40ns (scope measured)
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*/
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void fudelay(int usec)
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{
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while (usec--)
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asm volatile ("nop");
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}
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int dram_init(void)
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{
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u32 dramsize, RC;
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sdramctrl_t *dc = (sdramctrl_t *)(MMAP_DRAMC);
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/*
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* SDRAM MT48LC4M32B2 details
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* Memory block 0: 16 MB of SDRAM at address $00000000
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* Port size: 32-bit port
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*
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* Memory block 0 wired as follows:
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* CPU : A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23
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* SDRAM : A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1
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*
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* Ensure that there is a delay of at least 100 microseconds from
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* processor reset to the following code so that the SDRAM is ready
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* for commands.
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*/
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fudelay(100);
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/*
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* DCR
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* set proper RC as per specification
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*/
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RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1;
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RC = (RC * 15) >> 4;
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/* 0x8000 is the faster option */
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out_be16(&dc->dcr, 0x8200 | RC);
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/*
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* DACR0, page mode continuous, CMD on A20 0x0300
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*/
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out_be32(&dc->dacr0, 0x00003304);
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dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000;
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out_be32(&dc->dmr0, dramsize|1);
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/* issue a PRECHARGE ALL */
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out_be32(&dc->dacr0, 0x0000330c);
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out_be32((u32 *)0x00000004, 0xbeaddeed);
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/* issue AUTOREFRESH */
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out_be32(&dc->dacr0, 0x0000b304);
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/* let refresh occur */
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fudelay(1);
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out_be32(&dc->dacr0, 0x0000b344);
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out_be32((u32 *)0x00000c00, 0xbeaddeed);
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gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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static struct coldfire_serial_platdata mcf5307_serial_plat = {
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.base = CONFIG_SYS_UART_BASE,
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.port = 0,
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.baudrate = CONFIG_BAUDRATE,
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};
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U_BOOT_DEVICE(coldfire_serial) = {
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.name = "serial_coldfire",
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.platdata = &mcf5307_serial_plat,
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};
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