mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
28752cf83b
Use the U-Boot Driver Model. Just enable Freescale DSPI driver and set DSPI related parameters in dts file. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
186 lines
4.1 KiB
Text
186 lines
4.1 KiB
Text
/*
|
|
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
|
|
*
|
|
* Copyright (C) 2014-2015, Freescale Semiconductor
|
|
*
|
|
* Mingkai Hu <Mingkai.hu@freescale.com>
|
|
*
|
|
* This file is licensed under the terms of the GNU General Public
|
|
* License version 2. This program is licensed "as is" without any
|
|
* warranty of any kind, whether express or implied.
|
|
*/
|
|
|
|
/include/ "skeleton64.dtsi"
|
|
|
|
/ {
|
|
compatible = "fsl,ls1043a";
|
|
interrupt-parent = <&gic>;
|
|
cpus {
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
|
|
cpu0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x0 0x0>;
|
|
clocks = <&clockgen 1 0>;
|
|
};
|
|
|
|
cpu1: cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x0 0x1>;
|
|
clocks = <&clockgen 1 0>;
|
|
};
|
|
|
|
cpu2: cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x0 0x2>;
|
|
clocks = <&clockgen 1 0>;
|
|
};
|
|
|
|
cpu3: cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x0 0x3>;
|
|
clocks = <&clockgen 1 0>;
|
|
};
|
|
};
|
|
|
|
sysclk: sysclk {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <100000000>;
|
|
clock-output-names = "sysclk";
|
|
};
|
|
|
|
gic: interrupt-controller@1400000 {
|
|
compatible = "arm,gic-400";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
reg = <0x0 0x1401000 0 0x1000>, /* GICD */
|
|
<0x0 0x1402000 0 0x2000>, /* GICC */
|
|
<0x0 0x1404000 0 0x2000>, /* GICH */
|
|
<0x0 0x1406000 0 0x2000>; /* GICV */
|
|
interrupts = <1 9 0xf08>;
|
|
};
|
|
|
|
soc {
|
|
compatible = "simple-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
clockgen: clocking@1ee1000 {
|
|
compatible = "fsl,ls1043a-clockgen";
|
|
reg = <0x0 0x1ee1000 0x0 0x1000>;
|
|
#clock-cells = <2>;
|
|
clocks = <&sysclk>;
|
|
};
|
|
|
|
dspi0: dspi@2100000 {
|
|
compatible = "fsl,vf610-dspi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x2100000 0x0 0x10000>;
|
|
interrupts = <0 64 0x4>;
|
|
clock-names = "dspi";
|
|
clocks = <&clockgen 4 0>;
|
|
num-cs = <6>;
|
|
big-endian;
|
|
status = "disabled";
|
|
};
|
|
|
|
dspi1: dspi@2110000 {
|
|
compatible = "fsl,vf610-dspi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x2110000 0x0 0x10000>;
|
|
interrupts = <0 65 0x4>;
|
|
clock-names = "dspi";
|
|
clocks = <&clockgen 4 0>;
|
|
num-cs = <6>;
|
|
big-endian;
|
|
status = "disabled";
|
|
};
|
|
|
|
ifc: ifc@1530000 {
|
|
compatible = "fsl,ifc", "simple-bus";
|
|
reg = <0x0 0x1530000 0x0 0x10000>;
|
|
interrupts = <0 43 0x4>;
|
|
};
|
|
|
|
i2c0: i2c@2180000 {
|
|
compatible = "fsl,vf610-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x2180000 0x0 0x10000>;
|
|
interrupts = <0 56 0x4>;
|
|
clock-names = "i2c";
|
|
clocks = <&clockgen 4 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@2190000 {
|
|
compatible = "fsl,vf610-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x2190000 0x0 0x10000>;
|
|
interrupts = <0 57 0x4>;
|
|
clock-names = "i2c";
|
|
clocks = <&clockgen 4 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@21a0000 {
|
|
compatible = "fsl,vf610-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x21a0000 0x0 0x10000>;
|
|
interrupts = <0 58 0x4>;
|
|
clock-names = "i2c";
|
|
clocks = <&clockgen 4 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@21b0000 {
|
|
compatible = "fsl,vf610-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x21b0000 0x0 0x10000>;
|
|
interrupts = <0 59 0x4>;
|
|
clock-names = "i2c";
|
|
clocks = <&clockgen 4 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
duart0: serial@21c0500 {
|
|
compatible = "fsl,ns16550", "ns16550a";
|
|
reg = <0x00 0x21c0500 0x0 0x100>;
|
|
interrupts = <0 54 0x4>;
|
|
clocks = <&clockgen 4 0>;
|
|
};
|
|
|
|
duart1: serial@21c0600 {
|
|
compatible = "fsl,ns16550", "ns16550a";
|
|
reg = <0x00 0x21c0600 0x0 0x100>;
|
|
interrupts = <0 54 0x4>;
|
|
clocks = <&clockgen 4 0>;
|
|
};
|
|
|
|
duart2: serial@21d0500 {
|
|
compatible = "fsl,ns16550", "ns16550a";
|
|
reg = <0x0 0x21d0500 0x0 0x100>;
|
|
interrupts = <0 55 0x4>;
|
|
clocks = <&clockgen 4 0>;
|
|
};
|
|
|
|
duart3: serial@21d0600 {
|
|
compatible = "fsl,ns16550", "ns16550a";
|
|
reg = <0x0 0x21d0600 0x0 0x100>;
|
|
interrupts = <0 55 0x4>;
|
|
clocks = <&clockgen 4 0>;
|
|
};
|
|
};
|
|
};
|