mirror of
https://github.com/AsahiLinux/u-boot
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c05ed00afb
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
462 lines
13 KiB
C
462 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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*
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* (C) Copyright 2003
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* Texas Instruments, <www.ti.com>
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* Kshitij Gupta <Kshitij@ti.com>
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*
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* (C) Copyright 2004
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* ARM Ltd.
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* Philippe Robin, <philippe.robin@arm.com>
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*
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* (C) Copyright 2011
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* Linaro
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* Linus Walleij <linus.walleij@linaro.org>
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*/
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#include <common.h>
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#include <init.h>
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#include <log.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <linux/bug.h>
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#include <linux/delay.h>
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#include "integrator-sc.h"
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#include "pci_v3.h"
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#define INTEGRATOR_BOOT_ROM_BASE 0x20000000
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#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
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/*
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* These are in the physical addresses on the CPU side, i.e.
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* where we read and write stuff - you don't want to try to
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* move these around
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*/
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#define PHYS_PCI_MEM_BASE 0x40000000
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#define PHYS_PCI_IO_BASE 0x60000000 /* PCI I/O space base */
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#define PHYS_PCI_CONFIG_BASE 0x61000000
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#define PHYS_PCI_V3_BASE 0x62000000 /* V360EPC registers */
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#define SZ_256M 0x10000000
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/*
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* These are in the PCI BUS address space
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* Set to 0x00000000 in the Linux kernel, 0x40000000 in Boot monitor
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* we follow the example of the kernel, because that is the address
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* range that devices actually use - what would they be doing at
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* 0x40000000?
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*/
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#define PCI_BUS_NONMEM_START 0x00000000
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#define PCI_BUS_NONMEM_SIZE SZ_256M
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#define PCI_BUS_PREMEM_START (PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE)
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#define PCI_BUS_PREMEM_SIZE SZ_256M
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#if PCI_BUS_NONMEM_START & 0x000fffff
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#error PCI_BUS_NONMEM_START must be megabyte aligned
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#endif
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#if PCI_BUS_PREMEM_START & 0x000fffff
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#error PCI_BUS_PREMEM_START must be megabyte aligned
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#endif
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/*
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* Initialize PCI Devices, report devices found.
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*/
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#ifndef CONFIG_PCI_PNP
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#define PCI_ENET0_IOADDR 0x60000000 /* First card in PCI I/O space */
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#define PCI_ENET0_MEMADDR 0x40000000 /* First card in PCI memory space */
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static struct pci_config_table pci_integrator_config_table[] = {
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
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pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
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{ }
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};
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#endif /* CONFIG_PCI_PNP */
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/* V3 access routines */
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#define v3_writeb(o, v) __raw_writeb(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
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#define v3_readb(o) (__raw_readb(PHYS_PCI_V3_BASE + (unsigned int)(o)))
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#define v3_writew(o, v) __raw_writew(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
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#define v3_readw(o) (__raw_readw(PHYS_PCI_V3_BASE + (unsigned int)(o)))
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#define v3_writel(o, v) __raw_writel(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
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#define v3_readl(o) (__raw_readl(PHYS_PCI_V3_BASE + (unsigned int)(o)))
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static unsigned long v3_open_config_window(pci_dev_t bdf, int offset)
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{
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unsigned int address, mapaddress;
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unsigned int busnr = PCI_BUS(bdf);
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unsigned int devfn = PCI_FUNC(bdf);
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/*
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* Trap out illegal values
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*/
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if (offset > 255)
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BUG();
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if (busnr > 255)
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BUG();
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if (devfn > 255)
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BUG();
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if (busnr == 0) {
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/*
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* Linux calls the thing U-Boot calls "DEV" "SLOT"
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* instead, but it's the same 5 bits
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*/
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int slot = PCI_DEV(bdf);
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/*
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* local bus segment so need a type 0 config cycle
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*
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* build the PCI configuration "address" with one-hot in
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* A31-A11
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*
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* mapaddress:
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* 3:1 = config cycle (101)
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* 0 = PCI A1 & A0 are 0 (0)
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*/
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address = PCI_FUNC(bdf) << 8;
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mapaddress = V3_LB_MAP_TYPE_CONFIG;
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if (slot > 12)
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/*
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* high order bits are handled by the MAP register
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*/
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mapaddress |= 1 << (slot - 5);
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else
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/*
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* low order bits handled directly in the address
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*/
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address |= 1 << (slot + 11);
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} else {
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/*
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* not the local bus segment so need a type 1 config cycle
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*
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* address:
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* 23:16 = bus number
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* 15:11 = slot number (7:3 of devfn)
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* 10:8 = func number (2:0 of devfn)
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*
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* mapaddress:
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* 3:1 = config cycle (101)
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* 0 = PCI A1 & A0 from host bus (1)
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*/
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mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
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address = (busnr << 16) | (devfn << 8);
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}
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/*
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* Set up base0 to see all 512Mbytes of memory space (not
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* prefetchable), this frees up base1 for re-use by
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* configuration memory
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*/
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v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
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V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
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/*
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* Set up base1/map1 to point into configuration space.
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*/
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v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) |
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V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
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v3_writew(V3_LB_MAP1, mapaddress);
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return PHYS_PCI_CONFIG_BASE + address + offset;
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}
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static void v3_close_config_window(void)
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{
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/*
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* Reassign base1 for use by prefetchable PCI memory
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*/
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v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
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V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
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V3_LB_BASE_ENABLE);
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v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
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V3_LB_MAP_TYPE_MEM_MULTIPLE);
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/*
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* And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
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*/
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v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
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V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
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}
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static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t bdf,
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int offset, unsigned char *val)
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{
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unsigned long addr;
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addr = v3_open_config_window(bdf, offset);
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*val = __raw_readb(addr);
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v3_close_config_window();
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return 0;
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}
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static int pci_integrator_read__word(struct pci_controller *hose,
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pci_dev_t bdf, int offset,
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unsigned short *val)
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{
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unsigned long addr;
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addr = v3_open_config_window(bdf, offset);
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*val = __raw_readw(addr);
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v3_close_config_window();
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return 0;
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}
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static int pci_integrator_read_dword(struct pci_controller *hose,
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pci_dev_t bdf, int offset,
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unsigned int *val)
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{
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unsigned long addr;
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addr = v3_open_config_window(bdf, offset);
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*val = __raw_readl(addr);
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v3_close_config_window();
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return 0;
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}
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static int pci_integrator_write_byte(struct pci_controller *hose,
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pci_dev_t bdf, int offset,
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unsigned char val)
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{
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unsigned long addr;
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addr = v3_open_config_window(bdf, offset);
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__raw_writeb((u8)val, addr);
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__raw_readb(addr);
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v3_close_config_window();
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return 0;
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}
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static int pci_integrator_write_word(struct pci_controller *hose,
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pci_dev_t bdf, int offset,
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unsigned short val)
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{
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unsigned long addr;
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addr = v3_open_config_window(bdf, offset);
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__raw_writew((u8)val, addr);
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__raw_readw(addr);
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v3_close_config_window();
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return 0;
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}
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static int pci_integrator_write_dword(struct pci_controller *hose,
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pci_dev_t bdf, int offset,
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unsigned int val)
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{
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unsigned long addr;
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addr = v3_open_config_window(bdf, offset);
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__raw_writel((u8)val, addr);
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__raw_readl(addr);
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v3_close_config_window();
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return 0;
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}
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struct pci_controller integrator_hose = {
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#ifndef CONFIG_PCI_PNP
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config_table: pci_integrator_config_table,
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#endif
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};
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void pci_init_board(void)
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{
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struct pci_controller *hose = &integrator_hose;
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u16 val;
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/* setting this register will take the V3 out of reset */
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__raw_writel(SC_PCI_PCIEN, SC_PCI);
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/* Wait for 230 ms (from spec) before accessing any V3 registers */
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mdelay(230);
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/* Now write the Base I/O Address Word to PHYS_PCI_V3_BASE + 0x6E */
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v3_writew(V3_LB_IO_BASE, (PHYS_PCI_V3_BASE >> 16));
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/* Wait for the mailbox to settle */
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do {
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v3_writeb(V3_MAIL_DATA, 0xAA);
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v3_writeb(V3_MAIL_DATA + 4, 0x55);
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} while (v3_readb(V3_MAIL_DATA) != 0xAA ||
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v3_readb(V3_MAIL_DATA + 4) != 0x55);
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/* Make sure that V3 register access is not locked, if it is, unlock it */
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if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK)
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v3_writew(V3_SYSTEM, 0xA05F);
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/*
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* Ensure that the slave accesses from PCI are disabled while we
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* setup memory windows
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*/
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val = v3_readw(V3_PCI_CMD);
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val &= ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
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v3_writew(V3_PCI_CMD, val);
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/* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
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val = v3_readw(V3_SYSTEM);
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val &= ~V3_SYSTEM_M_RST_OUT;
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v3_writew(V3_SYSTEM, val);
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/* Make all accesses from PCI space retry until we're ready for them */
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val = v3_readw(V3_PCI_CFG);
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val |= V3_PCI_CFG_M_RETRY_EN;
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v3_writew(V3_PCI_CFG, val);
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/*
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* Set up any V3 PCI Configuration Registers that we absolutely have to.
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* LB_CFG controls Local Bus protocol.
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* Enable LocalBus byte strobes for READ accesses too.
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* set bit 7 BE_IMODE and bit 6 BE_OMODE
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*/
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val = v3_readw(V3_LB_CFG);
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val |= 0x0C0;
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v3_writew(V3_LB_CFG, val);
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/* PCI_CMD controls overall PCI operation. Enable PCI bus master. */
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val = v3_readw(V3_PCI_CMD);
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val |= V3_COMMAND_M_MASTER_EN;
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v3_writew(V3_PCI_CMD, val);
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/*
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* PCI_MAP0 controls where the PCI to CPU memory window is on
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* Local Bus
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*/
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v3_writel(V3_PCI_MAP0,
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(INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512MB |
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V3_PCI_MAP_M_REG_EN |
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V3_PCI_MAP_M_ENABLE));
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/* PCI_BASE0 is the PCI address of the start of the window */
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v3_writel(V3_PCI_BASE0, INTEGRATOR_BOOT_ROM_BASE);
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/* PCI_MAP1 is LOCAL address of the start of the window */
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v3_writel(V3_PCI_MAP1,
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(INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1GB |
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V3_PCI_MAP_M_REG_EN |
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V3_PCI_MAP_M_ENABLE));
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/* PCI_BASE1 is the PCI address of the start of the window */
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v3_writel(V3_PCI_BASE1, INTEGRATOR_HDR0_SDRAM_BASE);
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/*
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* Set up memory the windows from local bus memory into PCI
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* configuration, I/O and Memory regions.
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* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this.
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*/
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v3_writew(V3_LB_BASE2,
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v3_addr_to_lb_map(PHYS_PCI_IO_BASE) | V3_LB_BASE_ENABLE);
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v3_writew(V3_LB_MAP2, 0);
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/* PCI Configuration, use LB_BASE1/LB_MAP1. */
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/*
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* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1
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* Map first 256Mbytes as non-prefetchable via BASE0/MAP0
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*/
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v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
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V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
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v3_writew(V3_LB_MAP0,
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v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | V3_LB_MAP_TYPE_MEM);
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/* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
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v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
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V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
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V3_LB_BASE_ENABLE);
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v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
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V3_LB_MAP_TYPE_MEM_MULTIPLE);
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/* Dump PCI to local address space mappings */
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debug("LB_BASE0 = %08x\n", v3_readl(V3_LB_BASE0));
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debug("LB_MAP0 = %04x\n", v3_readw(V3_LB_MAP0));
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debug("LB_BASE1 = %08x\n", v3_readl(V3_LB_BASE1));
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debug("LB_MAP1 = %04x\n", v3_readw(V3_LB_MAP1));
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debug("LB_BASE2 = %04x\n", v3_readw(V3_LB_BASE2));
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debug("LB_MAP2 = %04x\n", v3_readw(V3_LB_MAP2));
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debug("LB_IO_BASE = %04x\n", v3_readw(V3_LB_IO_BASE));
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/*
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* Allow accesses to PCI Configuration space and set up A1, A0 for
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* type 1 config cycles
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*/
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val = v3_readw(V3_PCI_CFG);
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val &= ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1);
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val |= V3_PCI_CFG_M_AD_LOW0;
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v3_writew(V3_PCI_CFG, val);
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/* now we can allow incoming PCI MEMORY accesses */
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val = v3_readw(V3_PCI_CMD);
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val |= V3_COMMAND_M_MEM_EN;
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v3_writew(V3_PCI_CMD, val);
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/*
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* Set RST_OUT to take the PCI bus is out of reset, PCI devices can
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* now initialise.
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*/
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val = v3_readw(V3_SYSTEM);
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val |= V3_SYSTEM_M_RST_OUT;
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v3_writew(V3_SYSTEM, val);
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/* Lock the V3 system register so that no one else can play with it */
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val = v3_readw(V3_SYSTEM);
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val |= V3_SYSTEM_M_LOCK;
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v3_writew(V3_SYSTEM, val);
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/*
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* Configure and register the PCI hose
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*/
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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/* System memory space, window 0 256 MB non-prefetchable */
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pci_set_region(hose->regions + 0,
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PCI_BUS_NONMEM_START, PHYS_PCI_MEM_BASE,
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SZ_256M,
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PCI_REGION_MEM);
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/* System memory space, window 1 256 MB prefetchable */
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pci_set_region(hose->regions + 1,
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PCI_BUS_PREMEM_START, PHYS_PCI_MEM_BASE + SZ_256M,
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SZ_256M,
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PCI_REGION_MEM |
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PCI_REGION_PREFETCH);
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/* PCI I/O space */
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pci_set_region(hose->regions + 2,
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0x00000000, PHYS_PCI_IO_BASE, 0x01000000,
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PCI_REGION_IO);
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/* PCI Memory - config space */
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pci_set_region(hose->regions + 3,
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0x00000000, PHYS_PCI_CONFIG_BASE, 0x01000000,
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PCI_REGION_MEM);
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/* PCI V3 regs */
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pci_set_region(hose->regions + 4,
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0x00000000, PHYS_PCI_V3_BASE, 0x01000000,
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PCI_REGION_MEM);
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hose->region_count = 5;
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pci_set_ops(hose,
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pci_integrator_read_byte,
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pci_integrator_read__word,
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pci_integrator_read_dword,
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pci_integrator_write_byte,
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pci_integrator_write_word,
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pci_integrator_write_dword);
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pci_register_hose(hose);
|
|
|
|
pciauto_config_init(hose);
|
|
pciauto_config_device(hose, 0);
|
|
|
|
hose->last_busno = pci_hose_scan(hose);
|
|
}
|