mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-13 14:53:06 +00:00
6c869637fe
This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and changes the default from 8 to 1 for the legacy and the new MTD NAND layer. This allows to remove all NAND_MAX_CHIPS definitions in the board config files because none of the boards use multi chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440 define #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE but that's bogus and did not work anyhow. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
297 lines
12 KiB
C
297 lines
12 KiB
C
/*
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* (C) Copyright 2008
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* Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************************************
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* quad100hd.h - configuration for Quad100hd board
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***********************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_QUAD100HD 1 /* Board is Quad100hd */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_405EP 1 /* Specifc 405EP support*/
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define PLLMR0_DEFAULT PLLMR0_266_133_66 /* no PCI */
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#define PLLMR1_DEFAULT PLLMR1_266_133_66 /* no PCI */
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/* the environment is in the EEPROM by default */
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#define CONFIG_ENV_IS_IN_EEPROM
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#undef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_PPC4xx_EMAC
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#define CONFIG_NET_MULTI 1
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#define CONFIG_HAS_ETH1 1
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0x01 /* PHY address */
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#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
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#define CONFIG_PHY_RESET 1
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#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#undef CONFIG_CMD_ASKENV
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#undef CONFIG_CMD_CACHE
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#define CONFIG_CMD_DHCP
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#undef CONFIG_CMD_DIAG
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#define CONFIG_CMD_EEPROM
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#undef CONFIG_CMD_ELF
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#define CONFIG_CMD_I2C
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#undef CONFIG_CMD_IRQ
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#define CONFIG_CMD_JFFS2
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#undef CONFIG_CMD_LOG
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#undef CONFIG_CMD_MII
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#define CONFIG_CMD_NAND
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#undef CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*-----------------------------------------------------------------------
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* SDRAM
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*----------------------------------------------------------------------*/
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/*
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* SDRAM configuration (please see cpu/ppc/sdram.[ch])
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*/
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#define CONFIG_SDRAM_BANK0 1
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/* FIX! SDRAM timings used in datasheet */
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#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
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#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
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#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
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#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
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#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
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/*
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* JFFS2
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*/
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#define CONFIG_SYS_JFFS2_FIRST_BANK 0
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#ifdef CONFIG_SYS_KERNEL_IN_JFFS2
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#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0 /* JFFS starts at block 0 */
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#else /* kernel not in JFFS */
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#define CONFIG_SYS_JFFS2_FIRST_SECTOR 8 /* block 0-7 is kernel (1MB = 8 sectors) */
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#endif
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#define CONFIG_SYS_JFFS2_NUM_BANKS 1
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
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#define CONFIG_SYS_BASE_BAUD 691200
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SERIAL_MULTI
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/* The following table includes the supported baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
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/*-----------------------------------------------------------------------
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* Miscellaneous configurable options
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_LOOPW 1 /* enable loopw command */
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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/*-----------------------------------------------------------------------
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* I2C
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*----------------------------------------------------------------------*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* bytes of address */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 8 byte write page size */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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#define CONFIG_SYS_EEPROM_SIZE 0x2000
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0xFFC00000
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
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#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE)
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
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/* the environment is located before u-boot */
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#define CONFIG_ENV_ADDR (TEXT_BASE - CONFIG_ENV_SECT_SIZE)
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
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#endif
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#ifdef CONFIG_ENV_IS_IN_EEPROM
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#define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars */
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#define CONFIG_ENV_OFFSET 0x00000000
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#define CONFIG_SYS_ENABLE_CRC_16 1 /* Intrinsyc formatting used crc16 */
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#endif
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/* partly from PPCBoot */
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/* NAND */
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#define CONFIG_NAND
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#ifdef CONFIG_NAND
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#define CONFIG_SYS_NAND_BASE 0x60000000
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#define CONFIG_SYS_NAND_CS 10 /* our CS is GPIO10 */
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#define CONFIG_SYS_NAND_RDY 23 /* our RDY is GPIO23 */
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#define CONFIG_SYS_NAND_CE 24 /* our CE is GPIO24 */
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#define CONFIG_SYS_NAND_CLE 31 /* our CLE is GPIO31 */
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#define CONFIG_SYS_NAND_ALE 30 /* our ALE is GPIO30 */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#endif
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in data cache)
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*/
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/* use on chip memory (OCM) for temperary stack until sdram is tested */
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/* see ./cpu/ppc4xx/start.S */
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#define CONFIG_SYS_TEMP_STACK_OCM 1
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/* On Chip Memory location */
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#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
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#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM */
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#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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* Taken from PPCBoot board/icecube/icecube.h
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*/
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/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
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#define CONFIG_SYS_EBC_PB0AP 0x04002480
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/* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
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#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
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#define CONFIG_SYS_EBC_PB1AP 0x04005480
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#define CONFIG_SYS_EBC_PB1CR 0x60018000
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#define CONFIG_SYS_EBC_PB2AP 0x00000000
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#define CONFIG_SYS_EBC_PB2CR 0x00000000
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#define CONFIG_SYS_EBC_PB3AP 0x00000000
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#define CONFIG_SYS_EBC_PB3CR 0x00000000
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#define CONFIG_SYS_EBC_PB4AP 0x00000000
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#define CONFIG_SYS_EBC_PB4CR 0x00000000
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/*-----------------------------------------------------------------------
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* Definitions for GPIO setup (PPC405EP specific)
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*
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* Taken in part from PPCBoot board/icecube/icecube.h
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*/
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/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
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#define CONFIG_SYS_GPIO0_OSRH 0x55555550
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#define CONFIG_SYS_GPIO0_OSRL 0x00000110
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#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
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#define CONFIG_SYS_GPIO0_ISR1L 0x15555445
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#define CONFIG_SYS_GPIO0_TSRH 0x00000000
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#define CONFIG_SYS_GPIO0_TSRL 0x00000000
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#define CONFIG_SYS_GPIO0_TCR 0xFFFF8097
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#define CONFIG_SYS_GPIO0_ODR 0x00000000
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/* ENVIRONMENT VARS */
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#define CONFIG_IPADDR 192.168.1.67
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#define CONFIG_SERVERIP 192.168.1.50
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#define CONFIG_GATEWAYIP 192.168.1.1
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_LOADADDR 300000
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#endif /* __CONFIG_H */
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