mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 09:48:16 +00:00
700a0c648d
Old, obsolete and duplicated code was cleaned up and replace by the new partitioning method. There are two possible approaches now: * define a single, static partition * use mtdparts command line option and dynamic partitioning Default is static partitioning.
426 lines
13 KiB
C
426 lines
13 KiB
C
/*
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* (C) Copyright 2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC852T 1
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#define CONFIG_NC650 1
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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/*
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* 10 MHz - PLL input clock
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*/
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#define CONFIG_8xx_OSCLK 10000000
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/*
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* 50 MHz - default CPU clock
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*/
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#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
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/*
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* 15 MHz - CPU minimum clock
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*/
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#define CFG_8xx_CPUCLK_MIN 15000000
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/*
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* 133 MHz - CPU maximum clock
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*/
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#define CFG_8xx_CPUCLK_MAX 133000000
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#define CFG_MEASURE_CPUCLK
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#define CFG_8XX_XIN CONFIG_8xx_OSCLK
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"bootp;" \
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"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
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"bootm"
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#undef CONFIG_STATUS_LED /* Status LED disabled */
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
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#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
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#define FEC_ENET
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#define CONFIG_MII
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#define CFG_DISCOVER_PHY 1
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/* enable I2C and select the hardware/software driver */
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#undef CONFIG_HARD_I2C /* I2C with hardware support */
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#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
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#define CFG_I2C_SPEED 100000 /* 100 kHz */
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#define CFG_I2C_SLAVE 0x7f
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define SCL 0x1000 /* PA 3 */
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#define SDA 0x2000 /* PA 2 */
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#define PAR immr->im_ioport.iop_papar
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#define DIR immr->im_ioport.iop_padir
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#define DAT immr->im_ioport.iop_padat
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#define I2C_INIT {PAR &= ~(SCL | SDA); DIR |= SCL;}
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#define I2C_ACTIVE (DIR |= SDA)
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#define I2C_TRISTATE (DIR &= ~SDA)
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#define I2C_READ ((DAT & SDA) != 0)
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#define I2C_SDA(bit) if (bit) DAT |= SDA; \
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else DAT &= ~SDA
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#define I2C_SCL(bit) if (bit) DAT |= SCL; \
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else DAT &= ~SCL
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#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
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#define CONFIG_RTC_PCF8563
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#define CFG_I2C_RTC_ADDR 0x51
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_ASKENV | \
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CFG_CMD_DATE | \
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CFG_CMD_DHCP | \
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CFG_CMD_I2C | \
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CFG_CMD_NAND | \
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CFG_CMD_JFFS2 | \
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CFG_CMD_NFS | \
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CFG_CMD_SNTP )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
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#define CFG_LOAD_ADDR 0x00100000
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xF0000000
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#define CFG_IMMR_SIZE ((uint)(64 * 1024))
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0x40000000
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#define CFG_RESET_ADDRESS 0xFFF00100
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_OFFSET 0x00740000
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#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */
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#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*
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* NAND flash support
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*/
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#define CFG_MAX_NAND_DEVICE 1
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#define NAND_ChipID_UNKNOWN 0x00
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#define SECTORSIZE 512
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#define NAND_MAX_FLOORS 1
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#define NAND_MAX_CHIPS 1
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#define ADDR_PAGE 2
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#define ADDR_COLUMN_PAGE 3
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#define ADDR_COLUMN 1
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#define NAND_NO_RB
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#define NAND_WAIT_READY(nand) udelay(12)
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#define WRITE_NAND_COMMAND(d, adr) WRITE_NAND(d, adr + 2)
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#define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND(d, adr + 1)
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#define WRITE_NAND(d, adr) (*(volatile uint8_t *)(adr) = (uint8_t)(d))
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#define READ_NAND(adr) (*(volatile uint8_t *)(adr))
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#define NAND_DISABLE_CE(nand) /* nop */
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#define NAND_ENABLE_CE(nand) /* nop */
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#define NAND_CTL_CLRALE(nandptr) /* nop */
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#define NAND_CTL_SETALE(nandptr) /* nop */
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#define NAND_CTL_CLRCLE(nandptr) /* nop */
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#define NAND_CTL_SETCLE(nandptr) /* nop */
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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*/
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#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CFG_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF11
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#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | \
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SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
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SCCR_DFLCD000 | SCCR_DFALCD00)
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/*-----------------------------------------------------------------------
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*
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*-----------------------------------------------------------------------
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*
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*/
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#define CFG_DER 0
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/*
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* Init Memory Controller:
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*
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* BR0 and OR0 (FLASH)
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*/
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#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
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#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
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#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
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/* FLASH timing: Default value of OR0 after reset */
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#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
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OR_SCY_15_CLK | OR_TRLX)
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#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
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/*
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* BR2 and OR2 (NAND Flash) - now addressed through UPMB
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*/
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#define CFG_NAND_BASE 0x50000000
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#define CFG_NAND_SIZE 0x04000000
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#define CFG_OR_TIMING_NAND (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
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OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
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#define CFG_BR2_PRELIM ((CFG_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_UPMB | BR_V )
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#define CFG_OR2_PRELIM (((-CFG_NAND_SIZE) & OR_AM_MSK) | OR_BI )
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/*
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* BR3 and OR3 (SDRAM)
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*/
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#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
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#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
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/*
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* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)
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*/
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#define CFG_OR_TIMING_SDRAM 0x00000A00
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#define CFG_OR3_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
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#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
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/*
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* BR5 and OR5 (SRAM)
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*/
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#define CFG_SRAM_BASE 0x60000000
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#define CFG_SRAM_SIZE 0x00080000
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#define CFG_OR_TIMING_SRAM (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
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OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
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#define CFG_BR5_PRELIM ((CFG_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
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#define CFG_OR5_PRELIM (((-CFG_SRAM_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_SRAM)
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/*
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* 4096 Rows from SDRAM example configuration
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* 1000 factor s -> ms
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* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
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* 4 Number of refresh cycles per period
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* 64 Refresh cycle in ms per number of rows
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*/
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#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
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/*
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* Memory Periodic Timer Prescaler
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*/
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/* periodic timer for refresh */
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#define CFG_MAMR_PTA 39
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/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
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#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
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#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
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/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
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#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
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#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
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/*
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* MAMR settings for SDRAM
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*/
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#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
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MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
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#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
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MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
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/*
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* MBMR settings for NAND flash
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*/
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#define CFG_MBMR_NAND ( MBMR_WLFB_5X )
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
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#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
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/*
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* JFFS2 partitions
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*/
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/* No command line, one static partition */
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#undef CONFIG_JFFS2_CMDLINE
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#define CONFIG_JFFS2_DEV "nand0"
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#define CONFIG_JFFS2_PART_SIZE 0x00400000
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#define CONFIG_JFFS2_PART_OFFSET 0x00000000
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/* mtdparts command line support */
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/*
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#define CONFIG_JFFS2_CMDLINE
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#define MTDIDS_DEFAULT "nor0=nc650-0,nand0=nc650-nand"
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#define MTDPARTS_DEFAULT "mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \
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"2560k(cramfs1),2560k(cramfs2)," \
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"256k(u-boot),256k(env);" \
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"nc650-nand:4m(nand1),28m(nand2)"
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*/
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#endif /* __CONFIG_H */
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