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https://github.com/AsahiLinux/u-boot
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989ce04999
Add bcm281xx architecture support code including a clock framework and chip reset. Define register block base addresses for the bcm281xx architecture and create an empty gpio header file required when CONFIG_CMD_GPIO is set. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Steve Rae <srae@broadcom.com> Reviewed-by: Tim Kryger <tkryger@linaro.org>
52 lines
973 B
C
52 lines
973 B
C
/*
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* Copyright 2013 Broadcom Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/sysmap.h>
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#include <asm/kona-common/clk.h>
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#include "clk-core.h"
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/* Enable appropriate clocks for a BSC/I2C port */
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int clk_bsc_enable(void *base)
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{
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int ret;
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char *bscstr, *apbstr;
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switch ((u32) base) {
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case PMU_BSC_BASE_ADDR:
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/* PMU clock is always enabled */
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return 0;
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case BSC1_BASE_ADDR:
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bscstr = "bsc1_clk";
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apbstr = "bsc1_apb_clk";
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break;
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case BSC2_BASE_ADDR:
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bscstr = "bsc2_clk";
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apbstr = "bsc2_apb_clk";
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break;
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case BSC3_BASE_ADDR:
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bscstr = "bsc3_clk";
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apbstr = "bsc3_apb_clk";
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break;
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default:
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printf("%s: base 0x%p not found\n", __func__, base);
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return -EINVAL;
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}
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/* Note that the bus clock must be enabled first */
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ret = clk_get_and_enable(apbstr);
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if (ret)
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return ret;
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ret = clk_get_and_enable(bscstr);
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if (ret)
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return ret;
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return 0;
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}
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