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https://github.com/AsahiLinux/u-boot
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ccbd2ced73
In order to improve power consumption ls102x allows to disable peripherals that are not in use. This patch follows SELI8 HW design description and disables peripherals that are not in use in our designs, the same configuration is applicable and for EXPU1. This patch uses available hwconfig option for updating ls102x device disable configuration. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
307 lines
9.2 KiB
C
307 lines
9.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2020 Hitachi Power Grids. All rights reserved.
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*/
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#ifndef __CONFIG_PG_WCOM_LS102XA_H
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#define __CONFIG_PG_WCOM_LS102XA_H
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#define CONFIG_SYS_FSL_CLK
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/* include common defines/options for all Keymile boards */
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#include "keymile-common.h"
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
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#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
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#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + \
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CONFIG_KM_PHRAM + \
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CONFIG_KM_RESERVED_PRAM) >> 10)
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#define CONFIG_SYS_CLK_FREQ 66666666
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/*
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* Take into account default implementation where DDR_FDBK_MULTI is consider as
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* configured for DDR_PLL = 2*MEM_PLL_RAT.
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* In our case DDR_FDBK_MULTI is 2, means DDR_PLL = MEM_PLL_RAT.
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*/
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#define CONFIG_DDR_CLK_FREQ (100000000 >> 1)
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#define PHYS_SDRAM 0x80000000
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#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL 4
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#define CONFIG_DDR_SPD
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#define CONFIG_SYS_SPD_BUS_NUM 0
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#define SPD_EEPROM_ADDRESS 0x54
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/* POST memory regions test */
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#define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS)
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#define CONFIG_POST_EXTERNAL_WORD_FUNCS
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/*
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* IFC Definitions
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*/
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/* NOR Flash Definitions */
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#define CONFIG_FSL_IFC
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#define CONFIG_SYS_FLASH_BASE 0x60000000
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
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#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_TE | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024)
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#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | \
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CSOR_NOR_ADM_SHIFT(0x4) | \
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CSOR_NOR_NOR_MODE_ASYNC_NOR | \
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CSOR_NOR_TRHZ_20 | \
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CSOR_NOR_BCTLD)
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#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
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FTIM0_NOR_TEADC(0x7) | \
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FTIM0_NOR_TAVDS(0x0) | \
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FTIM0_NOR_TEAHC(0x1))
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#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
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FTIM1_NOR_TRAD_NOR(0x21) | \
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FTIM1_NOR_TSEQRAD_NOR(0x21))
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#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
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FTIM2_NOR_TCH(0x1) | \
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FTIM2_NOR_TWPH(0x6) | \
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FTIM2_NOR_TWP(0xb))
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#define CONFIG_SYS_NOR_FTIM3 0
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#define CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
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#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
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#define CONFIG_SYS_WRITE_SWAPPED_DATA
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
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/* NAND Flash Definitions */
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#define CONFIG_NAND_FSL_IFC
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#define CONFIG_SYS_NAND_BASE 0x68000000
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
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#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
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CSPR_PORT_SIZE_8 | \
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CSPR_TE | \
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CSPR_MSEL_NAND | \
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CSPR_V)
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#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
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#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
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| CSOR_NAND_ECC_DEC_EN \
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| CSOR_NAND_ECC_MODE_4 \
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| CSOR_NAND_RAL_3 \
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| CSOR_NAND_PGS_2K \
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| CSOR_NAND_SPRZ_64 \
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| CSOR_NAND_PB(64) \
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| CSOR_NAND_TRHZ_40 \
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| CSOR_NAND_BCTLD)
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
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FTIM0_NAND_TWP(0x8) | \
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FTIM0_NAND_TWCHT(0x3) | \
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FTIM0_NAND_TWH(0x5))
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#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
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FTIM1_NAND_TWBE(0x1e) | \
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FTIM1_NAND_TRR(0x6) | \
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FTIM1_NAND_TRP(0x8))
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#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
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FTIM2_NAND_TREH(0x5) | \
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FTIM2_NAND_TWHRE(0x3c))
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#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
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#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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/* QRIO FPGA Definitions */
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#define CONFIG_SYS_QRIO_BASE 0x70000000
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#define CONFIG_SYS_QRIO_BASE_PHYS CONFIG_SYS_QRIO_BASE
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#define CONFIG_SYS_CSPR2_EXT (0x00)
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#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
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CSPR_PORT_SIZE_8 | \
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CSPR_TE | \
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CSPR_MSEL_GPCM | \
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CSPR_V)
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#define CONFIG_SYS_AMASK2 IFC_AMASK(64 * 1024)
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#define CONFIG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \
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CSOR_GPCM_TRHZ_20 | \
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CSOR_GPCM_BCTLD)
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#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \
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FTIM0_GPCM_TEADC(0x8) | \
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FTIM0_GPCM_TEAHC(0x2))
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#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
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FTIM1_GPCM_TRAD(0x6))
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#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \
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FTIM2_GPCM_TCH(0x1) | \
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FTIM2_GPCM_TWP(0x7))
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#define CONFIG_SYS_CS2_FTIM3 0x04000000
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/*
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* Serial Port
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_CLK get_serial_clock()
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/*
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* I2C
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_INIT_BOARD
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_SYS_I2C_MAX_HOPS 1
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#define CONFIG_SYS_NUM_I2C_BUSES 3
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#define I2C_MUX_PCA_ADDR 0x70
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#define I2C_MUX_CH_DEFAULT 0x0
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#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
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{0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
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{1, {I2C_NULL_HOP} }, \
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}
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/*
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* eTSEC
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*/
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#ifdef CONFIG_TSEC_ENET
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#define CONFIG_ETHPRIME "ethernet@2d90000"
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#endif
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#define CONFIG_LAYERSCAPE_NS_ACCESS
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#define CONFIG_SMP_PEN_ADDR 0x01ee0200
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#define COUNTER_FREQUENCY 12500000
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 256
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#define CONFIG_FSL_DEVICE_DISABLE
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LOAD_ADDR 0x82000000
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#define CONFIG_LS102XA_STREAM_ID
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#define CONFIG_SYS_MONITOR_LEN 0x100000 /* 1Mbyte */
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#define CONFIG_SYS_QE_FW_ADDR 0x60020000
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#define CONFIG_SYS_BOOTCOUNT_BE
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/*
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* Environment
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*/
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#define CONFIG_ENV_TOTAL_SIZE 0x40000
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#define ENV_DEL_ADDR CONFIG_ENV_ADDR_REDUND /* direct for newenv */
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#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
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#define CONFIG_KM_DEF_ENV
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#endif
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#ifndef CONFIG_KM_DEF_BOOT_ARGS_CPU
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#define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
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#endif
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#define CONFIG_KM_DEF_ENV_CPU \
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"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
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"cramfsloadfdt=" \
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"cramfsload ${fdt_addr_r} " \
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"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
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"u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
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"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
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" +${filesize} && " \
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"erase " __stringify(CONFIG_SYS_MONITOR_BASE) \
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" +${filesize} && " \
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"cp.b ${load_addr_r} " \
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__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
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"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
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" +${filesize}\0" \
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"update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
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" +${filesize} && " \
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"erase " __stringify(CONFIG_SYS_FLASH_BASE) \
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" +${filesize} && " \
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"cp.b ${load_addr_r} " \
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__stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \
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"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
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" +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0" \
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"set_fdthigh=true\0" \
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"checkfdt=true\0" \
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""
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#define CONFIG_KM_NEW_ENV \
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"newenv=protect off " __stringify(ENV_DEL_ADDR) \
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" +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
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"erase " __stringify(ENV_DEL_ADDR) \
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" +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
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"protect on " __stringify(ENV_DEL_ADDR) \
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" +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
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#define CONFIG_HW_ENV_SETTINGS \
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"hwconfig=devdis:esdhc,usb3,usb2,sata,sec,dcu,duart2,qspi," \
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"can1,can2_4,ftm2_8,i2c2_3,sai1_4,lpuart2_6," \
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"asrc,spdif,lpuart1,ftm1\0"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_KM_NEW_ENV \
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CONFIG_KM_DEF_ENV \
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CONFIG_HW_ENV_SETTINGS \
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"EEprom_ivm=pca9547:70:9\0" \
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"ethrotate=no\0" \
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""
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */
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#endif
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