mirror of
https://github.com/AsahiLinux/u-boot
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86b116b1b1
Add the ability for modules from the Schindler cm5200 family to use a
single U-Boot image:
- rename cm1_qp1 to cm5200
- add run-time module detection
- parametrize SDRAM configuration according to the module we are running on
Few minor, board-specific fixes included in this patch:
- better MAC address handling
- updated default environment ('update' command uses +{filesize} now)
- improved error messages in the auto-update code
- allow booting U-Boot from RAM (CFG_RAMBOOT)
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
184 lines
4.4 KiB
C
184 lines
4.4 KiB
C
/*
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* (C) Copyright 2007 DENX Software Engineering
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*
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* Author: Bartlomiej Sieka <tur@semihalf.com>
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* Author: Grzegorz Bernacki <gjb@semihalf.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _CM5200_H
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#define _CM5200_H
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/*
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* Definitions and declarations for the modules of the cm5200 platform. Mostly
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* related to reading the hardware identification data (HW ID) from the I2C
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* EEPROM, detection of the particular module we are executing on, and
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* appropriate SDRAM controller initialization.
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*/
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#define CM5200_UNKNOWN_MODULE 0xffffffff
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enum {
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DEVICE_NAME, /* 0 */
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GENERATION, /* 1 */
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PCB_NAME, /* 2 */
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FORM, /* 3 */
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VERSION, /* 4 */
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IDENTIFICATION_NUMBER, /* 5 */
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MAJOR_SW_VERSION, /* 6 */
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MINOR_SW_VERSION, /* 7 */
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/* add new alements above this line */
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HW_ID_ELEM_COUNT /* count */
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};
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/*
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* Sect. 4.1 "CM1.Q/CMU1.Q Supervisory Microcontroller Interface Definition"
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*/
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#define DEVICE_NAME_OFFSET 0x02
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#define GENERATION_OFFSET 0x0b
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#define PCB_NAME_OFFSET 0x0c
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#define FORM_OFFSET 0x15
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#define VERSION_OFFSET 0x16
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#define IDENTIFICATION_NUMBER_OFFSET 0x19
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#define MAJOR_SW_VERSION_OFFSET 0x0480
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#define MINOR_SW_VERSION_OFFSET 0x0481
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#define DEVICE_NAME_LEN 0x09
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#define GENERATION_LEN 0x01
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#define PCB_NAME_LEN 0x09
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#define FORM_LEN 0x01
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#define VERSION_LEN 0x03
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#define IDENTIFICATION_NUMBER_LEN 0x09
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#define MAJOR_SW_VERSION_LEN 0x01
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#define MINOR_SW_VERSION_LEN 0x01
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#define HW_ID_ELEM_MAXLEN 0x09 /* MAX(XXX_LEN) */
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/* entire HW ID in EEPROM is 64 bytes, so longer module name is unlikely */
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#define MODULE_NAME_MAXLEN 64
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/* storage for HW ID read from EEPROM */
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typedef char hw_id_t[HW_ID_ELEM_COUNT][HW_ID_ELEM_MAXLEN];
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/* HW ID layout in EEPROM */
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static struct {
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unsigned int offset;
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unsigned int length;
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} hw_id_format[HW_ID_ELEM_COUNT] = {
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{DEVICE_NAME_OFFSET, DEVICE_NAME_LEN},
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{GENERATION_OFFSET, GENERATION_LEN},
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{PCB_NAME_OFFSET, PCB_NAME_LEN},
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{FORM_OFFSET, FORM_LEN},
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{VERSION_OFFSET, VERSION_LEN},
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{IDENTIFICATION_NUMBER_OFFSET, IDENTIFICATION_NUMBER_LEN},
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{MAJOR_SW_VERSION_OFFSET, MAJOR_SW_VERSION_LEN},
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{MINOR_SW_VERSION_OFFSET, MINOR_SW_VERSION_LEN},
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};
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/* HW ID data found in EEPROM on supported modules */
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static char *cm1_qa_hw_id[HW_ID_ELEM_COUNT] = {
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"CM", /* DEVICE_NAME */
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"1", /* GENERATION */
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"CM1", /* PCB_NAME */
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"Q", /* FORM */
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"A", /* VERSION */
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"591881", /* IDENTIFICATION_NUMBER */
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"", /* MAJOR_SW_VERSION */
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"", /* MINOR_SW_VERSION */
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};
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static char *cm11_qa_hw_id[HW_ID_ELEM_COUNT] = {
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"CM", /* DEVICE_NAME */
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"1", /* GENERATION */
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"CM11", /* PCB_NAME */
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"Q", /* FORM */
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"A", /* VERSION */
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"594200", /* IDENTIFICATION_NUMBER */
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"", /* MAJOR_SW_VERSION */
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"", /* MINOR_SW_VERSION */
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};
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static char *cmu1_qa_hw_id[HW_ID_ELEM_COUNT] = {
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"CMU", /* DEVICE_NAME */
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"1", /* GENERATION */
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"CMU1", /* PCB_NAME */
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"Q", /* FORM */
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"A", /* VERSION */
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"594128", /* IDENTIFICATION_NUMBER */
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"", /* MAJOR_SW_VERSION */
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"", /* MINOR_SW_VERSION */
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};
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/* list of known modules */
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static char **hw_id_list[] = {
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cm1_qa_hw_id,
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cm11_qa_hw_id,
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cmu1_qa_hw_id,
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};
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/* indices to the above list - keep in sync */
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enum {
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CM1_QA,
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CM11_QA,
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CMU1_QA,
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};
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/* identify modules based on these hw id elements */
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static int hw_id_identify[] = {
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PCB_NAME,
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FORM,
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VERSION,
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};
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/* Registers' settings for SDRAM controller intialization */
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typedef struct {
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ulong mode;
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ulong control;
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ulong config1;
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ulong config2;
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} mem_conf_t;
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static mem_conf_t k4s561632E = {
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0x00CD0000, /* CASL 3, burst length 8 */
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0x514F0000,
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0xE2333900,
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0x8EE70000
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};
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static mem_conf_t mt48lc32m16a2 = {
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0x00CD0000, /* CASL 3, burst length 8 */
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0x514F0000,
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0xD2322800,
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0x8AD70000
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};
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static mem_conf_t* memory_config[] = {
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&k4s561632E,
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&mt48lc32m16a2
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};
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#endif /* _CM5200_H */
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