u-boot/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
Sylvain Lemieux 89983478bd gpio: lpc32xx: fix issues with port3 gpio
The current simplify lpc32xx gpio driver implementation assume a
maximum of 32 GPIO per port; there are a total of 22 GPI, 24 GPO
and 6 GPIO to managed on port 3.

Update the driver to fix the following:
1) When requesting GPI_xx and GPO_xx on port 3 (xx is the same number)
   the second call to "gpio_request" will return -EBUSY.

2) The status of GPO_xx pin report the status of the
   corresponding GPI_xx pin when using the "gpio status" command.

3) The gpio driver may setup the direction register for the wrong
   gpio when calling "gpio_direction_input" (GPI_xx) or
   "gpio_direction_output" (GPO_xx) on port 3; the call to the
   direction is require to use the "gpio status" command.

The following change were done in the driver:
1) port3 GPI are cache in a separate 32 bits in the array.
2) port3 direction register written only for GPIO pins.
3) port3 GPO & GPIO (as output) are read using "p3_outp_state".
4) LPC32XX_GPI_P3_GRP updated to match the change.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2015-09-11 17:15:34 -04:00

40 lines
1.2 KiB
C

/*
* LPC32xx GPIO interface macro for pin mapping.
*
* (C) Copyright 2015 DENX Software Engineering GmbH
* Written-by: Sylvain Lemieux <slemieux@@tycoint.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _LPC32XX_GPIO_GRP_H
#define _LPC32XX_GPIO_GRP_H
/*
* Macro to map the pin for the lpc32xx_gpio driver.
* Note: - GPIOS are considered here as homogeneous and linear from 0 to 159;
* mapping is done per register, as group of 32.
* (see drivers/gpio/lpc32xx_gpio.c for details).
* - macros can be use with the following pins:
* P0.0 - P0.7
* P1.0 - P1.23
* P2.0 - P2.12
* P3 GPI_0 - GPI_9 / GPI_15 - GPI_23 / GPI_25 / GPI_27 - GPI_28
* P3 GPO_0 - GPO_23
* P3 GPIO_0 - GPIO_5 (output register only)
*/
#define LPC32XX_GPIO_P0_GRP 0
#define LPC32XX_GPIO_P1_GRP 32
#define LPC32XX_GPIO_P2_GRP 64
#define LPC32XX_GPO_P3_GRP 96
#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPO_P3_GRP + 25)
#define LPC32XX_GPI_P3_GRP 128
/*
* A specific GPIO can be selected with this macro
* ie, GPIO P0.1 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P0_GRP, 1)
* See the LPC32x0 User's guide for GPIO group numbers
*/
#define LPC32XX_GPIO(x, y) ((x) + (y))
#endif /* _LPC32XX_GPIO_GRP_H */