mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 02:38:56 +00:00
b841b6e946
Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com>
549 lines
12 KiB
ArmAsm
549 lines
12 KiB
ArmAsm
/*
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* Andesboot - Startup Code for Whitiger core
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*
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* Copyright (C) 2006 Andes Technology Corporation
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* Copyright (C) 2006 Shawn Lin <nobuhiro@andestech.com>
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* Copyright (C) 2011 Macpaul Lin <macpaul@andestech.com>
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* Greentime Hu <greentime@andestech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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.pic
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#include <asm-offsets.h>
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#include <config.h>
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#include <common.h>
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#include <asm/macro.h>
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/*
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* Jump vector table for EVIC mode
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*/
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#define ENA_DCAC 2UL
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#define DIS_DCAC ~ENA_DCAC
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#define ICAC_MEM_KBF_ISET (0x07) ! I Cache sets per way
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#define ICAC_MEM_KBF_IWAY (0x07<<3) ! I cache ways
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#define ICAC_MEM_KBF_ISZ (0x07<<6) ! I cache line size
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#define DCAC_MEM_KBF_DSET (0x07) ! D Cache sets per way
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#define DCAC_MEM_KBF_DWAY (0x07<<3) ! D cache ways
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#define DCAC_MEM_KBF_DSZ (0x07<<6) ! D cache line size
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#define PSW $ir0
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#define EIT_INTR_PSW $ir1 ! interruption $PSW
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#define EIT_PREV_IPSW $ir2 ! previous $IPSW
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#define EIT_IVB $ir3 ! intr vector base address
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#define EIT_EVA $ir4 ! MMU related Exception VA reg
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#define EIT_PREV_EVA $ir5 ! previous $eva
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#define EIT_ITYPE $ir6 ! interruption type
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#define EIT_PREV_ITYPE $ir7 ! prev intr type
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#define EIT_MACH_ERR $ir8 ! machine error log
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#define EIT_INTR_PC $ir9 ! Interruption PC
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#define EIT_PREV_IPC $ir10 ! previous $IPC
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#define EIT_OVL_INTR_PC $ir11 ! overflow interruption PC
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#define EIT_PREV_P0 $ir12 ! prev $P0
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#define EIT_PREV_P1 $ir13 ! prev $p1
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#define CR_ICAC_MEM $cr1 ! I-cache/memory config reg
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#define CR_DCAC_MEM $cr2 ! D-cache/memory config reg
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#define MR_CAC_CTL $mr8
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.globl _start
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_start: j reset
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j tlb_fill
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j tlb_not_present
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j tlb_misc
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j tlb_vlpt_miss
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j machine_error
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j debug
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j general_exception
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j syscall
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j internal_interrupt ! H0I
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j internal_interrupt ! H1I
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j internal_interrupt ! H2I
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j internal_interrupt ! H3I
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j internal_interrupt ! H4I
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j internal_interrupt ! H5I
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j software_interrupt ! S0I
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.balign 16
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/*
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* Andesboot Startup Code (reset vector)
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*
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* 1. bootstrap
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* 1.1 reset - start of u-boot
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* 1.2 to superuser mode - as is when reset
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* 1.4 Do lowlevel_init
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* - (this will jump out to lowlevel_init.S in SoC)
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* - (lowlevel_init)
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* 1.3 Turn off watchdog timer
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* - (this will jump out to watchdog.S in SoC)
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* - (turnoff_watchdog)
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* 2. Do critical init when reboot (not from mem)
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* 3. Relocate andesboot to ram
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* 4. Setup stack
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* 5. Jump to second stage (board_init_r)
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*/
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/* Note: TEXT_BASE is defined by the (board-dependent) linker script */
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.globl _TEXT_BASE
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_TEXT_BASE:
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.word CONFIG_SYS_TEXT_BASE
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/* IRQ stack memory (calculated at run-time) + 8 bytes */
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.globl IRQ_STACK_START_IN
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IRQ_STACK_START_IN:
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.word 0x0badc0de
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/*
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* The bootstrap code of nds32 core
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*/
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reset:
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/*
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* gp = ~0 for burn mode
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* = ~load_address for load mode
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*/
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reset_gp:
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.relax_hint 0
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sethi $gp, hi20(_GLOBAL_OFFSET_TABLE_-8)
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.relax_hint 0
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ori $gp, $gp, lo12(_GLOBAL_OFFSET_TABLE_-4)
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add5.pc $gp
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set_ivb:
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li $r0, 0x0
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/* turn on BTB */
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mtsr $r0, $misc_ctl
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/* set IVIC, vector size: 4 bytes, base: 0x0 */
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mtsr $r0, $ivb
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/*
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* MMU_CTL NTC0 Cacheable/Write-Back
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*/
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li $r0, ~0x3
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mfsr $r1, $mr8
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and $r1, $r1, $r0
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mtsr $r1, $mr8
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#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF))
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li $r0, 0x4
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mfsr $r1, $mr0
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or $r1, $r1, $r0
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mtsr $r1, $mr0
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#endif
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#if !defined(CONFIG_SYS_ICACHE_OFF)
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li $r0, 0x1
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mfsr $r1, $mr8
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or $r1, $r1, $r0
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mtsr $r1, $mr8
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#endif
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#if !defined(CONFIG_SYS_DCACHE_OFF)
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li $r0, 0x2
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mfsr $r1, $mr8
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or $r1, $r1, $r0
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mtsr $r1, $mr8
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#endif
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jal mem_init
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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jal lowlevel_init
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/*
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* gp = ~VMA for burn mode
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* = ~load_address for load mode
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*/
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update_gp:
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.relax_hint 0
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sethi $gp, hi20(_GLOBAL_OFFSET_TABLE_-8)
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.relax_hint 0
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ori $gp, $gp, lo12(_GLOBAL_OFFSET_TABLE_-4)
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add5.pc $gp
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#endif
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/*
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* do critical initializations first (shall be in short time)
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* do self_relocation ASAP.
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*/
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/*
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* Set the N1213 (Whitiger) core to superuser mode
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* According to spec, it is already when reset
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*/
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#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
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jal turnoff_watchdog
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#endif
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/*
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* Do CPU critical regs init only at reboot,
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* not when booting from ram
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*/
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#ifdef CONFIG_INIT_CRITICAL
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jal cpu_init_crit ! Do CPU critical regs init
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#endif
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/*
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* Set stackpointer in internal RAM to call board_init_f
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* $sp must be 8-byte alignment for ABI compliance.
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*/
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call_board_init_f:
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li $sp, CONFIG_SYS_INIT_SP_ADDR
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move $r0, $sp
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bal board_init_f_alloc_reserve
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move $sp, $r0
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bal board_init_f_init_reserve
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#ifdef CONFIG_DEBUG_UART
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bal debug_uart_init
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#endif
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li $r0, 0x00000000
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#ifdef __PIC__
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#ifdef __NDS32_N1213_43U1H__
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/* __NDS32_N1213_43U1H__ implies NDS32 V0 ISA */
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la $r15, board_init_f ! store function address into $r15
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#endif
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#endif
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j board_init_f ! jump to board_init_f() in lib/board.c
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/*
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* void relocate_code (addr_sp, gd, addr_moni)
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*
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* This "function" does not return, instead it continues in RAM
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* after relocating the monitor code.
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*
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*/
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/*
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* gp = ~RAM_SIZE - TEXT_SIZE for burn/load mode
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*/
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.globl relocate_code
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relocate_code:
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move $r4, $r0 /* save addr_sp */
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move $r5, $r1 /* save addr of gd */
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move $r6, $r2 /* save addr of destination */
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/* Set up the stack */
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stack_setup:
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move $sp, $r4
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la $r0, _start@GOTOFF
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beq $r0, $r6, clear_bss /* skip relocation */
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la $r1, _end@GOTOFF
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move $r2, $r6 /* r2 <- scratch for copy_loop */
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copy_loop:
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lmw.bim $r11, [$r0], $r18
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smw.bim $r11, [$r2], $r18
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blt $r0, $r1, copy_loop
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/*
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* fix relocations related issues
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*/
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fix_relocations:
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l.w $r0, _TEXT_BASE@GOTOFF /* r0 <- Text base */
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sub $r9, $r6, $r0 /* r9 <- relocation offset */
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la $r7, __rel_dyn_start@GOTOFF
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add $r7, $r7, $r9 /* r2 <- rel __got_start in RAM */
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la $r8, __rel_dyn_end@GOTOFF
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add $r8, $r8, $r9 /* r2 <- rel __got_start in RAM */
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li $r3, #0x2a /* R_NDS32_RELATIVE */
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1:
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lmw.bim $r0, [$r7], $r2 /* r0,r1,r2 <- adr,type,addend */
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bne $r1, $r3, 2f
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add $r0, $r0, $r9
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add $r2, $r2, $r9
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sw $r2, [$r0]
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2:
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blt $r7, $r8, 1b
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clear_bss:
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la $r0, __bss_start@GOTOFF /* r0 <- rel __bss_start in FLASH */
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add $r0, $r0, $r9 /* r0 <- rel __bss_start in FLASH */
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la $r1, __bss_end@GOTOFF /* r1 <- rel __bss_end in RAM */
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add $r1, $r1, $r9 /* r0 <- rel __bss_end in RAM */
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li $r2, 0x00000000 /* clear */
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clbss_l:
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sw $r2, [$r0] /* clear loop... */
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addi $r0, $r0, #4
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bne $r0, $r1, clbss_l
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/*
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* We are done. Do not return, instead branch to second part of board
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* initialization, now running from RAM.
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*/
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call_board_init_r:
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bal invalidate_icache_all
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bal flush_dcache_all
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la $r0, board_init_r@GOTOFF
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move $lp, $r0 /* offset of board_init_r() */
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add $lp, $lp, $r9 /* real address of board_init_r() */
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/* setup parameters for board_init_r */
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move $r0, $r5 /* gd_t */
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move $r1, $r6 /* dest_addr */
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#ifdef __PIC__
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#ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA */
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move $r15, $lp /* store function address into $r15 */
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#endif
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#endif
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/* jump to it ... */
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jr $lp /* jump to board_init_r() */
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/*
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* Initialize CPU critical registers
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*
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* 1. Setup control registers
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* 1.1 Mask all IRQs
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* 1.2 Flush cache and TLB
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* 1.3 Disable MMU and cache
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* 2. Setup memory timing
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*/
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cpu_init_crit:
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move $r0, $lp /* push ra */
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/* Disable Interrupts by clear GIE in $PSW reg */
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setgie.d
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/* Flush caches and TLB */
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/* Invalidate caches */
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jal invalidate_icac
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jal invalidate_dcac
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/* Flush TLB */
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mfsr $p0, $MMU_CFG
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andi $p0, $p0, 0x3 ! MMPS
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li $p1, 0x2 ! TLB MMU
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bne $p0, $p1, 1f
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tlbop flushall ! Flush TLB
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1:
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! Disable MMU, Dcache
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! Whitiger is MMU disabled when reset
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! Disable the D$
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mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg
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li $p1, DIS_DCAC
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and $p0, $p0, $p1 ! Set DC_EN bit
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mtsr $p0, MR_CAC_CTL ! write back the $CACHE_CTL reg
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isb
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move $lp, $r0
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2:
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ret
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/*
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* Invalidate I$
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*/
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invalidate_icac:
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! read $cr1(I CAC/MEM cfg. reg.) configuration
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mfsr $t0, CR_ICAC_MEM
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! Get the ISZ field
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andi $p0, $t0, ICAC_MEM_KBF_ISZ
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! if $p0=0, then no I CAC existed
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beqz $p0, end_flush_icache
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! get $p0 the index of I$ block
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srli $p0, $p0, 6
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! $t1= bit width of I cache line size(ISZ)
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addi $t1, $p0, 2
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li $t4, 1
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sll $t5, $t4, $t1 ! get $t5 cache line size
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andi $p1, $t0, ICAC_MEM_KBF_ISET ! get the ISET field
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addi $t2, $p1, 6 ! $t2= bit width of ISET
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andi $p1, $t0, ICAC_MEM_KBF_IWAY ! get bitfield of Iway
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srli $p1, $p1, 3
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addi $p1, $p1, 1 ! then $p1 is I way number
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add $t3, $t2, $t1 ! SHIFT
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sll $p1, $p1, $t3 ! GET the total cache size
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ICAC_LOOP:
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sub $p1, $p1, $t5
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cctl $p1, L1I_IX_INVAL
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bnez $p1, ICAC_LOOP
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end_flush_icache:
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ret
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/*
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* Invalidate D$
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*/
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invalidate_dcac:
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! read $cr2(D CAC/MEM cfg. reg.) configuration
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mfsr $t0, CR_DCAC_MEM
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! Get the DSZ field
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andi $p0, $t0, DCAC_MEM_KBF_DSZ
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! if $p0=0, then no D CAC existed
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beqz $p0, end_flush_dcache
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! get $p0 the index of D$ block
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srli $p0, $p0, 6
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! $t1= bit width of D cache line size(DSZ)
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addi $t1, $p0, 2
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li $t4, 1
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sll $t5, $t4, $t1 ! get $t5 cache line size
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andi $p1, $t0, DCAC_MEM_KBF_DSET ! get the DSET field
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addi $t2, $p1, 6 ! $t2= bit width of DSET
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andi $p1, $t0, DCAC_MEM_KBF_DWAY ! get bitfield of D way
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srli $p1, $p1, 3
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addi $p1, $p1, 1 ! then $p1 is D way number
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add $t3, $t2, $t1 ! SHIFT
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sll $p1, $p1, $t3 ! GET the total cache size
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DCAC_LOOP:
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sub $p1, $p1, $t5
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cctl $p1, L1D_IX_INVAL
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bnez $p1, DCAC_LOOP
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end_flush_dcache:
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ret
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/*
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* Interrupt handling
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*/
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/*
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* exception handlers
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*/
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.align 5
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.macro SAVE_ALL
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! FIXME: Other way to get PC?
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! FIXME: Update according to the newest spec!!
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1:
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li $r28, 1
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push $r28
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mfsr $r28, PSW ! $PSW
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push $r28
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mfsr $r28, EIT_EVA ! $ir1 $EVA
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push $r28
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mfsr $r28, EIT_ITYPE ! $ir2 $ITYPE
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push $r28
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mfsr $r28, EIT_MACH_ERR ! $ir3 Mach Error
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push $r28
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mfsr $r28, EIT_INTR_PSW ! $ir5 $IPSW
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push $r28
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mfsr $r28, EIT_PREV_IPSW ! $ir6 prev $IPSW
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push $r28
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mfsr $r28, EIT_PREV_EVA ! $ir7 prev $EVA
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push $r28
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mfsr $r28, EIT_PREV_ITYPE ! $ir8 prev $ITYPE
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push $r28
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mfsr $r28, EIT_INTR_PC ! $ir9 Interruption PC
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push $r28
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mfsr $r28, EIT_PREV_IPC ! $ir10 prev INTR_PC
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push $r28
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mfsr $r28, EIT_OVL_INTR_PC ! $ir11 Overflowed INTR_PC
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push $r28
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mfusr $r28, $d1.lo
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push $r28
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mfusr $r28, $d1.hi
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push $r28
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mfusr $r28, $d0.lo
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push $r28
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mfusr $r28, $d0.hi
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push $r28
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pushm $r0, $r30 ! store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp
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addi $sp, $sp, -4 ! make room for implicit pt_regs parameters
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.endm
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.align 5
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tlb_fill:
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SAVE_ALL
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move $r0, $sp ! To get the kernel stack
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li $r1, 1 ! Determine interruption type
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bal do_interruption
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.align 5
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tlb_not_present:
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SAVE_ALL
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move $r0, $sp ! To get the kernel stack
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li $r1, 2 ! Determine interruption type
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bal do_interruption
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.align 5
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tlb_misc:
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SAVE_ALL
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move $r0, $sp ! To get the kernel stack
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li $r1, 3 ! Determine interruption type
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bal do_interruption
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.align 5
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tlb_vlpt_miss:
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SAVE_ALL
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move $r0, $sp ! To get the kernel stack
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li $r1, 4 ! Determine interruption type
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bal do_interruption
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.align 5
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machine_error:
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SAVE_ALL
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move $r0, $sp ! To get the kernel stack
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li $r1, 5 ! Determine interruption type
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bal do_interruption
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.align 5
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debug:
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SAVE_ALL
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move $r0, $sp ! To get the kernel stack
|
|
li $r1, 6 ! Determine interruption type
|
|
bal do_interruption
|
|
|
|
.align 5
|
|
general_exception:
|
|
SAVE_ALL
|
|
move $r0, $sp ! To get the kernel stack
|
|
li $r1, 7 ! Determine interruption type
|
|
bal do_interruption
|
|
|
|
.align 5
|
|
syscall:
|
|
SAVE_ALL
|
|
move $r0, $sp ! To get the kernel stack
|
|
li $r1, 8 ! Determine interruption type
|
|
bal do_interruption
|
|
|
|
.align 5
|
|
internal_interrupt:
|
|
SAVE_ALL
|
|
move $r0, $sp ! To get the kernel stack
|
|
li $r1, 9 ! Determine interruption type
|
|
bal do_interruption
|
|
|
|
.align 5
|
|
software_interrupt:
|
|
SAVE_ALL
|
|
move $r0, $sp ! To get the kernel stack
|
|
li $r1, 10 ! Determine interruption type
|
|
bal do_interruption
|
|
|
|
.align 5
|
|
|
|
/*
|
|
* void reset_cpu(ulong addr);
|
|
* $r0: input address to jump to
|
|
*/
|
|
.globl reset_cpu
|
|
reset_cpu:
|
|
/* No need to disable MMU because we never enable it */
|
|
|
|
bal invalidate_icac
|
|
bal invalidate_dcac
|
|
mfsr $p0, $MMU_CFG
|
|
andi $p0, $p0, 0x3 ! MMPS
|
|
li $p1, 0x2 ! TLB MMU
|
|
bne $p0, $p1, 1f
|
|
tlbop flushall ! Flush TLB
|
|
1:
|
|
mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg
|
|
li $p1, DIS_DCAC
|
|
and $p0, $p0, $p1 ! Clear the DC_EN bit
|
|
mtsr $p0, MR_CAC_CTL ! Write back the $CACHE_CTL reg
|
|
br $r0 ! Jump to the input address
|