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b71eec3129
Intel Tunnel Creek GPIO register block is compatible with current ich6-gpio driver, except the offset and content of GPIO block base address register in the LPC PCI configuration space are different. Use u16 instead of u32 to store the 16-bit I/O address of the GPIO registers so that it could support both Ivybridge and Tunnel Creek. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
153 lines
2.8 KiB
C
153 lines
2.8 KiB
C
/*
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* Copyright (c) 2012, Google Inc. All rights reserved.
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _X86_GPIO_H_
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#define _X86_GPIO_H_
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#include <linux/compiler.h>
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#include <asm/arch/gpio.h>
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#include <asm-generic/gpio.h>
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struct ich6_bank_platdata {
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uint16_t base_addr;
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const char *bank_name;
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};
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#define GPIO_MODE_NATIVE 0
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#define GPIO_MODE_GPIO 1
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#define GPIO_MODE_NONE 1
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#define GPIO_DIR_OUTPUT 0
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#define GPIO_DIR_INPUT 1
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#define GPIO_NO_INVERT 0
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#define GPIO_INVERT 1
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#define GPIO_LEVEL_LOW 0
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#define GPIO_LEVEL_HIGH 1
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#define GPIO_NO_BLINK 0
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#define GPIO_BLINK 1
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#define GPIO_RESET_PWROK 0
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#define GPIO_RESET_RSMRST 1
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struct pch_gpio_set1 {
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u32 gpio0:1;
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u32 gpio1:1;
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u32 gpio2:1;
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u32 gpio3:1;
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u32 gpio4:1;
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u32 gpio5:1;
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u32 gpio6:1;
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u32 gpio7:1;
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u32 gpio8:1;
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u32 gpio9:1;
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u32 gpio10:1;
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u32 gpio11:1;
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u32 gpio12:1;
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u32 gpio13:1;
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u32 gpio14:1;
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u32 gpio15:1;
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u32 gpio16:1;
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u32 gpio17:1;
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u32 gpio18:1;
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u32 gpio19:1;
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u32 gpio20:1;
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u32 gpio21:1;
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u32 gpio22:1;
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u32 gpio23:1;
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u32 gpio24:1;
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u32 gpio25:1;
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u32 gpio26:1;
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u32 gpio27:1;
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u32 gpio28:1;
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u32 gpio29:1;
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u32 gpio30:1;
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u32 gpio31:1;
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} __packed;
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struct pch_gpio_set2 {
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u32 gpio32:1;
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u32 gpio33:1;
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u32 gpio34:1;
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u32 gpio35:1;
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u32 gpio36:1;
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u32 gpio37:1;
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u32 gpio38:1;
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u32 gpio39:1;
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u32 gpio40:1;
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u32 gpio41:1;
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u32 gpio42:1;
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u32 gpio43:1;
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u32 gpio44:1;
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u32 gpio45:1;
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u32 gpio46:1;
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u32 gpio47:1;
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u32 gpio48:1;
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u32 gpio49:1;
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u32 gpio50:1;
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u32 gpio51:1;
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u32 gpio52:1;
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u32 gpio53:1;
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u32 gpio54:1;
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u32 gpio55:1;
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u32 gpio56:1;
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u32 gpio57:1;
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u32 gpio58:1;
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u32 gpio59:1;
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u32 gpio60:1;
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u32 gpio61:1;
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u32 gpio62:1;
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u32 gpio63:1;
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} __packed;
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struct pch_gpio_set3 {
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u32 gpio64:1;
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u32 gpio65:1;
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u32 gpio66:1;
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u32 gpio67:1;
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u32 gpio68:1;
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u32 gpio69:1;
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u32 gpio70:1;
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u32 gpio71:1;
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u32 gpio72:1;
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u32 gpio73:1;
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u32 gpio74:1;
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u32 gpio75:1;
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} __packed;
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/*
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* This hilariously complex structure came from Coreboot. The
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* setup_pch_gpios() function uses it. It could be move to device tree, or
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* adjust to use masks instead of bitfields.
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*/
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struct pch_gpio_map {
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struct {
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const struct pch_gpio_set1 *mode;
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const struct pch_gpio_set1 *direction;
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const struct pch_gpio_set1 *level;
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const struct pch_gpio_set1 *reset;
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const struct pch_gpio_set1 *invert;
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const struct pch_gpio_set1 *blink;
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} set1;
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struct {
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const struct pch_gpio_set2 *mode;
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const struct pch_gpio_set2 *direction;
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const struct pch_gpio_set2 *level;
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const struct pch_gpio_set2 *reset;
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} set2;
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struct {
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const struct pch_gpio_set3 *mode;
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const struct pch_gpio_set3 *direction;
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const struct pch_gpio_set3 *level;
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const struct pch_gpio_set3 *reset;
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} set3;
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};
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void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
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void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
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#endif /* _X86_GPIO_H_ */
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