mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-30 16:39:35 +00:00
26750c8aee
We provide a default table of { 9600, 19200, 38400, 57600, 115200 }
in <config_fallbacks.h> which mkconfig places after <configs/...h> in
the generated config file. This is used when a board has not set its
own table.
Signed-off-by: Tom Rini <trini@ti.com>
205 lines
6.9 KiB
C
205 lines
6.9 KiB
C
/*
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* Authors: Xiangfu Liu <xiangfu.z@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 3 of the License, or (at your option) any later version.
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*/
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#ifndef __CONFIG_QI_LB60_H
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#define __CONFIG_QI_LB60_H
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#define CONFIG_MIPS32 /* MIPS32 CPU core */
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#define CONFIG_JZSOC /* Jz SoC */
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#define CONFIG_JZ4740 /* Jz4740 SoC */
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#define CONFIG_NAND_JZ4740
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#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
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#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
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#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */
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#define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_SYS_CPU_SPEED
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#define CONFIG_SYS_UART_BASE JZ4740_UART0_BASE /* Base of the UART channel */
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#define CONFIG_BAUDRATE 57600
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_SYS_FLASH_BASE 0 /* init flash_base as 0 */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
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#define CONFIG_BOOTDELAY 0
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#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
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#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
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/*
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* Command line configuration.
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*/
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#define CONFIG_CMD_BOOTD /* bootd */
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#define CONFIG_CMD_CONSOLE /* coninfo */
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#define CONFIG_CMD_ECHO /* echo arguments */
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#define CONFIG_CMD_LOADB /* loadb */
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#define CONFIG_CMD_LOADS /* loads */
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#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
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#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
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#define CONFIG_CMD_RUN /* run command in env variable */
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#define CONFIG_CMD_SAVEENV /* saveenv */
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#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
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#define CONFIG_CMD_SOURCE /* "source" command support */
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#define CONFIG_CMD_NAND
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/*
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* Serial download configuration
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*/
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_PROMPT "NanoNote# "
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
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#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
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#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
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#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
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#define CONFIG_SYS_LOAD_ADDR 0x80600000
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#define CONFIG_SYS_MEMTEST_START 0x80100000
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#define CONFIG_SYS_MEMTEST_END 0x80800000
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/*
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* Environment
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*/
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#define CONFIG_ENV_IS_IN_NAND /* use NAND for environment vars */
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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/*
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* if board nand flash is 1GB, set to 1
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* if board nand flash is 2GB, set to 2
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* for change the PAGE_SIZE and BLOCK_SIZE
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* will delete when there is no 1GB flash
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*/
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#define NANONOTE_NAND_SIZE 2
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#define CONFIG_SYS_NAND_PAGE_SIZE (2048 * NANONOTE_NAND_SIZE)
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#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * NANONOTE_NAND_SIZE << 10)
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/* nand bad block was marked at this page in a block, start from 0 */
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#define CONFIG_SYS_NAND_BADBLOCK_PAGE 127
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#define CONFIG_SYS_NAND_PAGE_COUNT 128
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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/* ECC offset position in oob area, default value is 6 if it isn't defined */
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#define CONFIG_SYS_NAND_ECC_POS (6 * NANONOTE_NAND_SIZE)
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 9
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#define CONFIG_SYS_NAND_ECCPOS \
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{12, 13, 14, 15, 16, 17, 18, 19,\
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20, 21, 22, 23, 24, 25, 26, 27, \
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28, 29, 30, 31, 32, 33, 34, 35, \
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36, 37, 38, 39, 40, 41, 42, 43, \
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44, 45, 46, 47, 48, 49, 50, 51, \
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52, 53, 54, 55, 56, 57, 58, 59, \
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60, 61, 62, 63, 64, 65, 66, 67, \
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68, 69, 70, 71, 72, 73, 74, 75, \
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76, 77, 78, 79, 80, 81, 82, 83}
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#define CONFIG_SYS_NAND_OOBSIZE 128
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#define CONFIG_SYS_NAND_BASE 0xB8000000
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#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
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#define CONFIG_NAND_SPL_TEXT_BASE 0x80000000
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/*
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* IPL (Initial Program Loader, integrated inside CPU)
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* Will load first 8k from NAND (SPL) into cache and execute it from there.
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*
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* SPL (Secondary Program Loader)
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* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
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* has to fit into 8kByte. It sets up the CPU and configures the SDRAM
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* controller and the NAND controller so that the special U-Boot image can be
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* loaded from NAND to SDRAM.
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*
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* NUB (NAND U-Boot)
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* This NAND U-Boot (NUB) is a special U-Boot version which can be started
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* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
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*
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*/
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#define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
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/* Start NUB from this addr*/
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/*
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* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
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*/
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#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
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#define CONFIG_ENV_SIZE (4 << 10)
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#define CONFIG_ENV_OFFSET \
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(CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE)
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#define CONFIG_ENV_OFFSET_REDUND \
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(CONFIG_ENV_OFFSET + CONFIG_SYS_NAND_BLOCK_SIZE)
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#define CONFIG_SYS_TEXT_BASE 0x80100000
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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/*
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* SDRAM Info.
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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/*
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* Cache Configuration
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*/
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#define CONFIG_SYS_DCACHE_SIZE 16384
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#define CONFIG_SYS_ICACHE_SIZE 16384
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#define CONFIG_SYS_CACHELINE_SIZE 32
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/*
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* GPIO definition
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*/
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#define GPIO_LCD_CS (2 * 32 + 21)
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#define GPIO_AMP_EN (3 * 32 + 4)
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#define GPIO_SDPW_EN (3 * 32 + 2)
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#define GPIO_SD_DETECT (3 * 32 + 0)
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#define GPIO_BUZZ_PWM (3 * 32 + 27)
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#define GPIO_USB_DETECT (3 * 32 + 28)
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#define GPIO_AUDIO_POP (1 * 32 + 29)
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#define GPIO_COB_TEST (1 * 32 + 30)
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#define GPIO_KEYOUT_BASE (2 * 32 + 10)
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#define GPIO_KEYIN_BASE (3 * 32 + 18)
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#define GPIO_KEYIN_8 (3 * 32 + 26)
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#define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */
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#define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */
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#define SPEN GPIO_LCD_CS /* LCDCS :Serial command enable */
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#define SPDA (2 * 32 + 22) /* LCDSCL:Serial command clock input */
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#define SPCK (2 * 32 + 23) /* LCDSDA:Serial command data input */
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/* SDRAM paramters */
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#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
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#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
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#define SDRAM_ROW 13 /* Row address: 11 to 13 */
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#define SDRAM_COL 9 /* Column address: 8 to 12 */
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#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
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/* SDRAM Timings, unit: ns */
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#define SDRAM_TRAS 45 /* RAS# Active Time */
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#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
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#define SDRAM_TPC 20 /* RAS# Precharge Time */
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#define SDRAM_TRWL 7 /* Write Latency Time */
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#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
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#endif
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