mirror of
https://github.com/AsahiLinux/u-boot
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781 lines
22 KiB
C
781 lines
22 KiB
C
/*
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* (C) Copyright 2007
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* Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
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*
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* (C) Copyright 2003
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* Juergen Beisert, EuroDesign embedded technologies, info@eurodsn.de
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* Derived from walnut.c
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* $Log:$
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include "sc3.h"
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#include <pci.h>
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#include <i2c.h>
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#include <malloc.h>
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#undef writel
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#undef writeb
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#define writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
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#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
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/* write only register to configure things in our CPLD */
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#define CPLD_CONTROL_1 0x79000102
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#define CPLD_VERSION 0x79000103
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#define IS_CAMERON ((*(unsigned char *)(CPLD_VERSION)== 0x32) ? 1 : 0)
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static struct pci_controller hose={0,};
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/************************************************************
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* Standard definition
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************************************************************/
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/* CPC0_CR0 Function ISA bus
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- GPIO0
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- GPIO1 -> Output: NAND-Command Latch Enable
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- GPIO2 -> Output: NAND Address Latch Enable
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- GPIO3 -> IRQ input ISA-IRQ #5 (through CPLD)
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- GPIO4 -> Output: NAND-Chip Enable
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- GPIO5 -> IRQ input ISA-IRQ#7 (through CPLD)
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- GPIO6 -> IRQ input ISA-IRQ#9 (through CPLD)
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- GPIO7 -> IRQ input ISA-IRQ#10 (through CPLD)
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- GPIO8 -> IRQ input ISA-IRQ#11 (through CPLD)
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- GPIO9 -> IRQ input ISA-IRQ#12 (through CPLD)
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- GPIO10/CS1# -> CS1# NAND ISA-CS#0
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- GPIO11/CS2# -> CS2# ISA emulation ISA-CS#1
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- GPIO12/CS3# -> CS3# 2nd Flash-Bank ISA-CS#2 or ISA-CS#7
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- GPIO13/CS4# -> CS4# USB HC or ISA emulation ISA-CS#3
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- GPIO14/CS5# -> CS5# Boosted IDE access ISA-CS#4
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- GPIO15/CS6# -> CS6# ISA emulation ISA-CS#5
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- GPIO16/CS7# -> CS7# ISA emulation ISA-CS#6
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- GPIO17/IRQ0 -> GPIO, in, NAND-Ready/Busy# line ISA-IRQ#3
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- GPIO18/IRQ1 -> IRQ input ISA-IRQ#14
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- GPIO19/IRQ2 -> IRQ input or USB ISA-IRQ#4
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- GPIO20/IRQ3 -> IRQ input PCI-IRQ#D
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- GPIO21/IRQ4 -> IRQ input PCI-IRQ#C
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- GPIO22/IRQ5 -> IRQ input PCI-IRQ#B
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- GPIO23/IRQ6 -> IRQ input PCI-IRQ#A
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- GPIO24 -> if GPIO output: 0=JTAG CPLD activ, 1=JTAG CPLD inactiv
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*/
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/*
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| CPLD register: io-space at offset 0x102 (write only)
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| 0
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| 1
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| 2 0=CS#4 USB CS#, 1=ISA or GP bus
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| 3
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| 4
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| 5
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| 6 1=enable faster IDE access
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| 7
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*/
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#define USB_CHIP_ENABLE 0x04
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#define IDE_BOOSTING 0x40
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/* --------------- USB stuff ------------------------------------- */
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#ifdef CONFIG_ISP1161_PRESENT
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/**
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* initUsbHost- Initialize the Philips isp1161 HC part if present
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* @cpldConfig: Pointer to value in write only CPLD register
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*
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* Initialize the USB host controller if present and fills the
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* scratch register to inform the driver about used resources
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*/
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static void initUsbHost (unsigned char *cpldConfig)
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{
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int i;
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unsigned long usbBase;
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/*
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* Read back where init.S has located the USB chip
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*/
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mtdcr (0x012, 0x04);
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usbBase = mfdcr (0x013);
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if (!(usbBase & 0x18000)) /* enabled? */
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return;
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usbBase &= 0xFFF00000;
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/*
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* to test for the USB controller enable using of CS#4 and DMA 3 for USB access
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*/
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writeb (*cpldConfig | USB_CHIP_ENABLE,CPLD_CONTROL_1);
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/*
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* first check: is the controller assembled?
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*/
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hcWriteWord (usbBase, 0x5555, HcScratch);
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if (hcReadWord (usbBase, HcScratch) == 0x5555) {
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hcWriteWord (usbBase, 0xAAAA, HcScratch);
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if (hcReadWord (usbBase, HcScratch) == 0xAAAA) {
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if ((hcReadWord (usbBase, HcChipID) & 0xFF00) != 0x6100)
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return; /* this is not our controller */
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/*
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* try a software reset. This needs up to 10 seconds (see datasheet)
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*/
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hcWriteDWord (usbBase, 0x00000001, HcCommandStatus);
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for (i = 1000; i > 0; i--) { /* loop up to 10 seconds */
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udelay (10);
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if (!(hcReadDWord (usbBase, HcCommandStatus) & 0x01))
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break;
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}
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if (!i)
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return; /* the controller doesn't responding. Broken? */
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/*
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* OK. USB controller is ready. Initialize it in such way the later driver
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* can us it (without any knowing about specific implementation)
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*/
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hcWriteDWord (usbBase, 0x00000000, HcControl);
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/*
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* disable all interrupt sources. Because we
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* don't know where we come from (hard reset, cold start, soft reset...)
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*/
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hcWriteDWord (usbBase, 0x8000007D, HcInterruptDisable);
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/*
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* our current setup hardware configuration
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* - every port power supply can switched indepently
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* - every port can signal overcurrent
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* - every port is "outside" and the devices are removeable
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*/
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hcWriteDWord (usbBase, 0x32000902, HcRhDescriptorA);
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hcWriteDWord (usbBase, 0x00060000, HcRhDescriptorB);
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/*
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* don't forget to switch off power supply of each port
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* The later running driver can reenable them to find and use
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* the (maybe) connected devices.
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*
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*/
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hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus1);
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hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus2);
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hcWriteWord (usbBase, 0x0428, HcHardwareConfiguration);
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hcWriteWord (usbBase, 0x0040, HcDMAConfiguration);
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hcWriteWord (usbBase, 0x0000, HcuPInterruptEnable);
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hcWriteWord (usbBase, 0xA000 | (0x03 << 8) | 27, HcScratch);
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/*
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* controller is present and usable
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*/
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*cpldConfig |= USB_CHIP_ENABLE;
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}
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}
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}
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#endif
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#if defined(CONFIG_START_IDE)
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int board_start_ide(void)
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{
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if (IS_CAMERON) {
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puts ("no IDE on cameron board.\n");
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return 0;
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}
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return 1;
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}
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#endif
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static int sc3_cameron_init (void)
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{
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/* Set up the Memory Controller for the CAMERON version */
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mtebc (pb4ap, 0x01805940);
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mtebc (pb4cr, 0x7401a000);
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mtebc (pb5ap, 0x01805940);
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mtebc (pb5cr, 0x7401a000);
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mtebc (pb6ap, 0x0);
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mtebc (pb6cr, 0x0);
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mtebc (pb7ap, 0x0);
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mtebc (pb7cr, 0x0);
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return 0;
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}
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void sc3_read_eeprom (void)
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{
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uchar i2c_buffer[18];
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i2c_read (0x50, 0x03, 1, i2c_buffer, 9);
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i2c_buffer[9] = 0;
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setenv ("serial#", (char *)i2c_buffer);
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/* read mac-address from eeprom */
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i2c_read (0x50, 0x11, 1, i2c_buffer, 15);
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i2c_buffer[17] = 0;
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i2c_buffer[16] = i2c_buffer[14];
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i2c_buffer[15] = i2c_buffer[13];
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i2c_buffer[14] = ':';
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i2c_buffer[13] = i2c_buffer[12];
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i2c_buffer[12] = i2c_buffer[11];
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i2c_buffer[11] = ':';
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i2c_buffer[8] = ':';
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i2c_buffer[5] = ':';
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i2c_buffer[2] = ':';
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setenv ("ethaddr", (char *)i2c_buffer);
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}
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int board_early_init_f (void)
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{
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/* write only register to configure things in our CPLD */
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unsigned char cpldConfig_1=0x00;
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/*-------------------------------------------------------------------------+
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| Interrupt controller setup for the SolidCard III CPU card (plus Evaluation board).
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| Note: IRQ 0 UART 0, active high; level sensitive
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| IRQ 1 UART 1, active high; level sensitive
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| IRQ 2 IIC, active high; level sensitive
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| IRQ 3 Ext. master, rising edge, edge sensitive
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| IRQ 4 PCI, active high; level sensitive
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| IRQ 5 DMA Channel 0, active high; level sensitive
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| IRQ 6 DMA Channel 1, active high; level sensitive
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| IRQ 7 DMA Channel 2, active high; level sensitive
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| IRQ 8 DMA Channel 3, active high; level sensitive
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| IRQ 9 Ethernet Wakeup, active high; level sensitive
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| IRQ 10 MAL System Error (SERR), active high; level sensitive
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| IRQ 11 MAL Tx End of Buffer, active high; level sensitive
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| IRQ 12 MAL Rx End of Buffer, active high; level sensitive
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| IRQ 13 MAL Tx Descriptor Error, active high; level sensitive
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| IRQ 14 MAL Rx Descriptor Error, active high; level sensitive
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| IRQ 15 Ethernet, active high; level sensitive
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| IRQ 16 External PCI SERR, active high; level sensitive
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| IRQ 17 ECC Correctable Error, active high; level sensitive
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| IRQ 18 PCI Power Management, active high; level sensitive
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| IRQ 19 (EXT IRQ7 405GPr only)
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| IRQ 20 (EXT IRQ8 405GPr only)
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| IRQ 21 (EXT IRQ9 405GPr only)
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| IRQ 22 (EXT IRQ10 405GPr only)
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| IRQ 23 (EXT IRQ11 405GPr only)
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| IRQ 24 (EXT IRQ12 405GPr only)
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| IRQ 25 (EXT IRQ 0) NAND-Flash R/B# (raising edge means flash is ready)
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| IRQ 26 (EXT IRQ 1) IDE0 interrupt (x86 = IRQ14). Active high (edge sensitive)
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| IRQ 27 (EXT IRQ 2) USB controller
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| IRQ 28 (EXT IRQ 3) INT D, VGA; active low; level sensitive
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| IRQ 29 (EXT IRQ 4) INT C, Ethernet; active low; level sensitive
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| IRQ 30 (EXT IRQ 5) INT B, PC104+ SLOT; active low; level sensitive
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| IRQ 31 (EXT IRQ 6) INT A, PC104+ SLOT; active low; level sensitive
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| Direct Memory Access Controller Signal Polarities
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| DRQ0 active high (like ISA)
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| ACK0 active low (like ISA)
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| EOT0 active high (like ISA)
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| DRQ1 active high (like ISA)
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| ACK1 active low (like ISA)
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| EOT1 active high (like ISA)
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| DRQ2 active high (like ISA)
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| ACK2 active low (like ISA)
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| EOT2 active high (like ISA)
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| DRQ3 active high (like ISA)
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| ACK3 active low (like ISA)
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| EOT3 active high (like ISA)
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+-------------------------------------------------------------------------*/
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writeb (cpldConfig_1, CPLD_CONTROL_1); /* disable everything in CPLD */
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mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr (uicer, 0x00000000); /* disable all ints */
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mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
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if (IS_CAMERON) {
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sc3_cameron_init();
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mtdcr (0x0B6, 0x18000000);
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mtdcr (uicpr, 0xFFFFFFF0);
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mtdcr (uictr, 0x10001030);
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} else {
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mtdcr (0x0B6, 0x0000000);
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mtdcr (uicpr, 0xFFFFFFE0);
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mtdcr (uictr, 0x10000020);
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}
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mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
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mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
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/* setup other implementation specific details */
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mtdcr (ecr, 0x60606000);
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mtdcr (cntrl1, 0x000042C0);
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if (IS_CAMERON) {
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mtdcr (cntrl0, 0x01380000);
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/* Setup the GPIOs */
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writel (0x08008000, 0xEF600700); /* Output states */
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writel (0x00000000, 0xEF600718); /* Open Drain control */
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writel (0x68098000, 0xEF600704); /* Output control */
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} else {
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mtdcr (cntrl0,0x00080000);
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/* Setup the GPIOs */
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writel (0x08000000, 0xEF600700); /* Output states */
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writel (0x14000000, 0xEF600718); /* Open Drain control */
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writel (0x7C000000, 0xEF600704); /* Output control */
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}
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/* Code decompression disabled */
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mtdcr (kiar, kconf);
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mtdcr (kidr, 0x2B);
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/* CPC0_ER: enable sleep mode of (currently) unused components */
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/* CPC0_FR: force unused components into sleep mode */
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mtdcr (cpmer, 0x3F800000);
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mtdcr (cpmfr, 0x14000000);
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/* set PLB priority */
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mtdcr (0x87, 0x08000000);
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/* --------------- DMA stuff ------------------------------------- */
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mtdcr (0x126, 0x49200000);
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#ifndef IDE_USES_ISA_EMULATION
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cpldConfig_1 |= IDE_BOOSTING; /* enable faster IDE */
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/* cpldConfig |= 0x01; */ /* enable 8.33MHz output, if *not* present on your baseboard */
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writeb (cpldConfig_1, CPLD_CONTROL_1);
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#endif
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#ifdef CONFIG_ISP1161_PRESENT
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initUsbHost (&cpldConfig_1);
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writeb (cpldConfig_1, CPLD_CONTROL_1);
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#endif
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/* FIXME: for what must we do this */
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*(unsigned long *)0x79000080 = 0x0001;
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return(0);
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}
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int misc_init_r (void)
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{
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char *s1;
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int i, xilinx_val;
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volatile char *xilinx_adr;
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xilinx_adr = (char *)0x79000102;
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*xilinx_adr = 0x00;
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/* customer settings ***************************************** */
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/*
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s1 = getenv ("function");
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if (s1) {
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if (!strcmp (s1, "Rosho")) {
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printf ("function 'Rosho' activated\n");
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*xilinx_adr = 0x40;
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}
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else {
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printf (">>>>>>>>>> function %s not recognized\n",s1);
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}
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}
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*/
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/* individual settings ***************************************** */
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if ((s1 = getenv ("xilinx"))) {
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i=0;
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xilinx_val = 0;
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while (i < 3 && s1[i]) {
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if (s1[i] >= '0' && s1[i] <= '9')
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xilinx_val = (xilinx_val << 4) + s1[i] - '0';
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else
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if (s1[i] >= 'A' && s1[i] <= 'F')
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xilinx_val = (xilinx_val << 4) + s1[i] - 'A' + 10;
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else
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if (s1[i] >= 'a' && s1[i] <= 'f')
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xilinx_val = (xilinx_val << 4) + s1[i] - 'a' + 10;
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else {
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xilinx_val = -1;
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break;
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}
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i++;
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}
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if (xilinx_val >= 0 && xilinx_val <=255 && i < 3) {
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printf ("Xilinx: set to %s\n", s1);
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*xilinx_adr = (unsigned char) xilinx_val;
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} else
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printf ("Xilinx: rejected value %s\n", s1);
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}
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return 0;
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}
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/* -------------------------------------------------------------------------
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* printCSConfig
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*
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* Print some informations about chips select configurations
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* Only used while debugging.
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*
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* Params:
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* - No. of CS pin
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* - AP of this CS
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* - CR of this CS
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*
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* Returns
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* nothing
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------------------------------------------------------------------------- */
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#ifdef SC3_DEBUGOUT
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static void printCSConfig(int reg,unsigned long ap,unsigned long cr)
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{
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const char *bsize[4] = {"8","16","32","?"};
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const unsigned char banks[8] = {1, 2, 4, 8, 16, 32, 64, 128};
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const char *bankaccess[4] = {"disabled", "RO", "WO", "RW"};
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#define CYCLE 30 /* time of one clock (based on 33MHz) */
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printf("\nCS#%d",reg);
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if (!(cr & 0x00018000))
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puts(" unused");
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else {
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if (((cr&0xFFF00000U) & ((banks[(cr & 0x000E0000) >> 17]-1) << 20)))
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puts(" Address is not multiple of bank size!");
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printf("\n -%s bit device",
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bsize[(cr & 0x00006000) >> 13]);
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printf(" at 0x%08lX", cr & 0xFFF00000U);
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printf(" size: %u MB", banks[(cr & 0x000E0000) >> 17]);
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printf(" rights: %s", bankaccess[(cr & 0x00018000) >> 15]);
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if (ap & 0x80000000) {
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printf("\n -Burst device (%luns/%luns)",
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(((ap & 0x7C000000) >> 26) + 1) * CYCLE,
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(((ap & 0x03800000) >> 23) + 1) * CYCLE);
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} else {
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printf("\n -Non burst device, active cycle %luns",
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(((ap & 0x7F800000) >> 23) + 1) * CYCLE);
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printf("\n -Address setup %luns",
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((ap & 0xC0000) >> 18) * CYCLE);
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printf("\n -CS active to RD %luns/WR %luns",
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((ap & 0x30000) >> 16) * CYCLE,
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((ap & 0xC000) >> 14) * CYCLE);
|
|
printf("\n -WR to CS inactive %luns",
|
|
((ap & 0x3000) >> 12) * CYCLE);
|
|
printf("\n -Hold after access %luns",
|
|
((ap & 0xE00) >> 9) * CYCLE);
|
|
printf("\n -Ready is %sabled",
|
|
ap & 0x100 ? "en" : "dis");
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#ifdef SC3_DEBUGOUT
|
|
|
|
static unsigned int ap[] = {pb0ap, pb1ap, pb2ap, pb3ap, pb4ap,
|
|
pb5ap, pb6ap, pb7ap};
|
|
static unsigned int cr[] = {pb0cr, pb1cr, pb2cr, pb3cr, pb4cr,
|
|
pb5cr, pb6cr, pb7cr};
|
|
|
|
static int show_reg (int nr)
|
|
{
|
|
unsigned long ul1, ul2;
|
|
|
|
mtdcr (ebccfga, ap[nr]);
|
|
ul1 = mfdcr (ebccfgd);
|
|
mtdcr (ebccfga, cr[nr]);
|
|
ul2 = mfdcr(ebccfgd);
|
|
printCSConfig(nr, ul1, ul2);
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int checkboard (void)
|
|
{
|
|
#ifdef SC3_DEBUGOUT
|
|
unsigned long ul1;
|
|
int i;
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
show_reg (i);
|
|
}
|
|
|
|
mtdcr (ebccfga, epcr);
|
|
ul1 = mfdcr (ebccfgd);
|
|
|
|
puts ("\nGeneral configuration:\n");
|
|
|
|
if (ul1 & 0x80000000)
|
|
printf(" -External Bus is always driven\n");
|
|
|
|
if (ul1 & 0x400000)
|
|
printf(" -CS signals are always driven\n");
|
|
|
|
if (ul1 & 0x20000)
|
|
printf(" -PowerDown after %lu clocks\n",
|
|
(ul1 & 0x1F000) >> 7);
|
|
|
|
switch (ul1 & 0xC0000)
|
|
{
|
|
case 0xC0000:
|
|
printf(" -No external master present\n");
|
|
break;
|
|
case 0x00000:
|
|
printf(" -8 bit external master present\n");
|
|
break;
|
|
case 0x40000:
|
|
printf(" -16 bit external master present\n");
|
|
break;
|
|
case 0x80000:
|
|
printf(" -32 bit external master present\n");
|
|
break;
|
|
}
|
|
|
|
switch (ul1 & 0x300000)
|
|
{
|
|
case 0x300000:
|
|
printf(" -Prefetch: Illegal setting!\n");
|
|
break;
|
|
case 0x000000:
|
|
printf(" -1 doubleword prefetch\n");
|
|
break;
|
|
case 0x100000:
|
|
printf(" -2 doublewords prefetch\n");
|
|
break;
|
|
case 0x200000:
|
|
printf(" -4 doublewords prefetch\n");
|
|
break;
|
|
}
|
|
putc ('\n');
|
|
#endif
|
|
printf("Board: SolidCard III %s %s version.\n",
|
|
(IS_CAMERON ? "Cameron" : "Eurodesign"), CONFIG_SC3_VERSION);
|
|
return 0;
|
|
}
|
|
|
|
static int printSDRAMConfig(char reg, unsigned long cr)
|
|
{
|
|
const int bisize[8]={4, 8, 16, 32, 64, 128, 256, 0};
|
|
#ifdef SC3_DEBUGOUT
|
|
const char *basize[8]=
|
|
{"4", "8", "16", "32", "64", "128", "256", "Reserved"};
|
|
|
|
printf("SDRAM bank %d",reg);
|
|
|
|
if (!(cr & 0x01))
|
|
puts(" disabled\n");
|
|
else {
|
|
printf(" at 0x%08lX, size %s MB",cr & 0xFFC00000,basize[(cr&0xE0000)>>17]);
|
|
printf(" mode %lu\n",((cr & 0xE000)>>13)+1);
|
|
}
|
|
#endif
|
|
|
|
if (cr & 0x01)
|
|
return(bisize[(cr & 0xE0000) >> 17]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef SC3_DEBUGOUT
|
|
static unsigned int mbcf[] = {mem_mb0cf, mem_mb1cf, mem_mb2cf, mem_mb3cf};
|
|
#endif
|
|
|
|
long int initdram (int board_type)
|
|
{
|
|
unsigned int mems=0;
|
|
unsigned long ul1;
|
|
|
|
#ifdef SC3_DEBUGOUT
|
|
unsigned long ul2;
|
|
int i;
|
|
|
|
puts("\nSDRAM configuration:\n");
|
|
|
|
mtdcr (memcfga, mem_mcopt1);
|
|
ul1 = mfdcr(memcfgd);
|
|
|
|
if (!(ul1 & 0x80000000)) {
|
|
puts(" Controller disabled\n");
|
|
return 0;
|
|
}
|
|
for (i = 0; i < 4; i++) {
|
|
mtdcr (memcfga, mbcf[i]);
|
|
ul1 = mfdcr (memcfgd);
|
|
mems += printSDRAMConfig (i, ul1);
|
|
}
|
|
|
|
mtdcr (memcfga, mem_sdtr1);
|
|
ul1 = mfdcr(memcfgd);
|
|
|
|
printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1);
|
|
printf (" -Precharge %lu (PTA) \n", ((ul1 & 0xC0000) >> 18) + 1);
|
|
printf (" -R/W to Precharge %lu (CTP)\n", ((ul1 & 0x30000) >> 16) + 1);
|
|
printf (" -Leadoff %lu\n", ((ul1 & 0xC000) >> 14) + 1);
|
|
printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4);
|
|
printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1));
|
|
puts ("Misc:\n");
|
|
mtdcr (memcfga, mem_rtr);
|
|
ul1 = mfdcr(memcfgd);
|
|
printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7);
|
|
|
|
mtdcr(memcfga,mem_pmit);
|
|
ul2=mfdcr(memcfgd);
|
|
|
|
mtdcr(memcfga,mem_mcopt1);
|
|
ul1=mfdcr(memcfgd);
|
|
|
|
if (ul1 & 0x20000000)
|
|
printf(" -Power Down after: %luns\n",
|
|
((ul2 & 0xFFC00000) >> 22) * 7);
|
|
else
|
|
puts(" -Power Down disabled\n");
|
|
|
|
if (ul1 & 0x40000000)
|
|
printf(" -Self refresh feature active\n");
|
|
else
|
|
puts(" -Self refresh disabled\n");
|
|
|
|
if (ul1 & 0x10000000)
|
|
puts(" -ECC enabled\n");
|
|
else
|
|
puts(" -ECC disabled\n");
|
|
|
|
if (ul1 & 0x8000000)
|
|
puts(" -Using registered SDRAM\n");
|
|
|
|
if (!(ul1 & 0x6000000))
|
|
puts(" -Using 32 bit data width\n");
|
|
else
|
|
puts(" -Illegal data width!\n");
|
|
|
|
if (ul1 & 0x400000)
|
|
puts(" -ECC drivers inactive\n");
|
|
else
|
|
puts(" -ECC drivers active\n");
|
|
|
|
if (ul1 & 0x200000)
|
|
puts(" -Memory lines always active outputs\n");
|
|
else
|
|
puts(" -Memory lines only at write cycles active outputs\n");
|
|
|
|
mtdcr (memcfga, mem_status);
|
|
ul1 = mfdcr (memcfgd);
|
|
if (ul1 & 0x80000000)
|
|
puts(" -SDRAM Controller ready\n");
|
|
else
|
|
puts(" -SDRAM Controller not ready\n");
|
|
|
|
if (ul1 & 0x4000000)
|
|
puts(" -SDRAM in self refresh mode!\n");
|
|
|
|
return (mems * 1024 * 1024);
|
|
#else
|
|
mtdcr (memcfga, mem_mb0cf);
|
|
ul1 = mfdcr (memcfgd);
|
|
mems = printSDRAMConfig (0, ul1);
|
|
|
|
mtdcr (memcfga, mem_mb1cf);
|
|
ul1 = mfdcr (memcfgd);
|
|
mems += printSDRAMConfig (1, ul1);
|
|
|
|
mtdcr (memcfga, mem_mb2cf);
|
|
ul1 = mfdcr(memcfgd);
|
|
mems += printSDRAMConfig (2, ul1);
|
|
|
|
mtdcr (memcfga, mem_mb3cf);
|
|
ul1 = mfdcr(memcfgd);
|
|
mems += printSDRAMConfig (3, ul1);
|
|
|
|
return (mems * 1024 * 1024);
|
|
#endif
|
|
}
|
|
|
|
static void pci_solidcard3_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
|
|
{
|
|
/*-------------------------------------------------------------------------+
|
|
| ,-. ,-. ,-. ,-. ,-.
|
|
| INTD# ----|B|-----|P|-. ,-|P|-. ,-| |-. ,-|G|
|
|
| |R| |C| \ / |C| \ / |E| \ / |r|
|
|
| INTC# ----|I|-----|1|-. `/---|1|-. `/---|t|-. `/---|a|
|
|
| |D| |0| \/ |0| \/ |h| \/ |f|
|
|
| INTB# ----|G|-----|4|-./`----|4|-./`----|e|-./`----|i|
|
|
| |E| |+| /\ |+| /\ |r| /\ |k|
|
|
| INTA# ----| |-----| |- `----| |- `----| |- `----| |
|
|
| `-' `-' `-' `-' `-'
|
|
| Slot 0 10 11 12 13
|
|
| REQ# 0 1 2 *
|
|
| GNT# 0 1 2 *
|
|
+-------------------------------------------------------------------------*/
|
|
unsigned char int_line = 0xff;
|
|
|
|
switch (PCI_DEV(dev)) {
|
|
case 10:
|
|
int_line = 31; /* INT A */
|
|
POST_OUT(0x42);
|
|
break;
|
|
|
|
case 11:
|
|
int_line = 30; /* INT B */
|
|
POST_OUT(0x43);
|
|
break;
|
|
|
|
case 12:
|
|
int_line = 29; /* INT C */
|
|
POST_OUT(0x44);
|
|
break;
|
|
|
|
case 13:
|
|
int_line = 28; /* INT D */
|
|
POST_OUT(0x45);
|
|
break;
|
|
}
|
|
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
|
|
}
|
|
|
|
extern void pci_405gp_init(struct pci_controller *hose);
|
|
extern void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev);
|
|
extern void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,struct pci_config_table *entry);
|
|
/*
|
|
* The following table is used when there is a special need to setup a PCI device.
|
|
* For every PCI device found in this table is called the given init function with given
|
|
* parameters. So never let all IDs at PCI_ANY_ID. In this case any found device gets the same
|
|
* parameters!
|
|
*
|
|
*/
|
|
static struct pci_config_table pci_solidcard3_config_table[] =
|
|
{
|
|
/* Host to PCI Bridge device (405GP) */
|
|
{
|
|
vendor: 0x1014,
|
|
device: 0x0156,
|
|
class: PCI_CLASS_BRIDGE_HOST,
|
|
bus: 0,
|
|
dev: 0,
|
|
func: 0,
|
|
config_device: pci_405gp_setup_bridge
|
|
},
|
|
{ }
|
|
};
|
|
|
|
/*-------------------------------------------------------------------------+
|
|
| pci_init_board (Called from pci_init() in drivers/pci/pci.c)
|
|
|
|
|
| Init the PCI part of the SolidCard III
|
|
|
|
|
| Params:
|
|
* - Pointer to current PCI hose
|
|
* - Current Device
|
|
*
|
|
* Returns
|
|
* nothing
|
|
+-------------------------------------------------------------------------*/
|
|
|
|
void pci_init_board(void)
|
|
{
|
|
POST_OUT(0x41);
|
|
/*
|
|
* we want the ptrs to RAM not flash (ie don't use init list)
|
|
*/
|
|
hose.fixup_irq = pci_solidcard3_fixup_irq;
|
|
hose.config_table = pci_solidcard3_config_table;
|
|
pci_405gp_init(&hose);
|
|
}
|