mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-25 00:42:21 +00:00
2f8a6db5d8
In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com>
203 lines
5.5 KiB
C
203 lines
5.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Based on davinci_dvevm.h. Original Copyrights follow:
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* Board
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*/
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/*
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* SoC Configuration
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*/
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#define CONFIG_SYS_OSCIN_FREQ 24000000
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#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
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#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
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/*
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* Memory Info
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*/
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#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
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#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
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#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
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#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
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#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
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/* memtest start addr */
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/* memtest will be run on 16MB */
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#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
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DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
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DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
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DAVINCI_SYSCFG_SUSPSRC_UART2 | \
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DAVINCI_SYSCFG_SUSPSRC_EMAC | \
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DAVINCI_SYSCFG_SUSPSRC_I2C)
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/*
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* PLL configuration
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*/
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/* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
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#define CONFIG_SYS_DA850_PLL0_PLLM 18
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#define CONFIG_SYS_DA850_PLL1_PLLM 21
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/*
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* DDR2 memory configuration
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*/
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#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
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DV_DDR_PHY_EXT_STRBEN | \
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(0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
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#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
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(1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
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(1 << DV_DDR_SDCR_DDREN_SHIFT) | \
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(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
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(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
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(4 << DV_DDR_SDCR_CL_SHIFT) | \
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(3 << DV_DDR_SDCR_IBANK_SHIFT) | \
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(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
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/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
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#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
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#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
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(19 << DV_DDR_SDTMR1_RFC_SHIFT) | \
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(1 << DV_DDR_SDTMR1_RP_SHIFT) | \
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(1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
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(2 << DV_DDR_SDTMR1_WR_SHIFT) | \
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(6 << DV_DDR_SDTMR1_RAS_SHIFT) | \
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(8 << DV_DDR_SDTMR1_RC_SHIFT) | \
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(1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
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(1 << DV_DDR_SDTMR1_WTR_SHIFT))
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#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
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(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
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(2 << DV_DDR_SDTMR2_XP_SHIFT) | \
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(0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
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(20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
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(199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
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(1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
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(2 << DV_DDR_SDTMR2_CKE_SHIFT))
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#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492
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#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
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/*
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* Serial Driver info
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*/
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#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
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#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
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#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
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/*
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* I2C Configuration
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*/
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#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
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#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
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#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
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/*
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* Flash & Environment
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*/
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#ifdef CONFIG_MTD_RAW_NAND
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#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
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#define CONFIG_SYS_NAND_PAGE_2K
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#define CONFIG_SYS_NAND_CS 3
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#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
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#define CONFIG_SYS_NAND_MASK_CLE 0x10
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#define CONFIG_SYS_NAND_MASK_ALE 0x8
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#undef CONFIG_SYS_NAND_HW_ECC
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
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#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
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#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
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#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
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#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
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CONFIG_SYS_NAND_U_BOOT_SIZE - \
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CONFIG_SYS_MALLOC_LEN - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_NAND_ECCPOS { \
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6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
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22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
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38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
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54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 10
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#endif
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/*
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* Network & Ethernet Configuration
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*/
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#ifdef CONFIG_DRIVER_TI_EMAC
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#define CONFIG_NET_RETRY_COUNT 10
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#endif
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/*
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* U-Boot general configuration
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*/
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#define CONFIG_BOOTFILE "zImage" /* Boot file name */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
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/*
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* USB Configs
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*/
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
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/*
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* Linux Information
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*/
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#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
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#define DEFAULT_LINUX_BOOT_ENV \
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"loadaddr=0xc0700000\0" \
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"fdtaddr=0xc0600000\0" \
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"scriptaddr=0xc0600000\0"
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#include <environment/ti/mmc.h>
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#define CONFIG_EXTRA_ENV_SETTINGS \
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DEFAULT_LINUX_BOOT_ENV \
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DEFAULT_MMC_TI_ARGS \
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"bootpart=0:2\0" \
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"bootdir=/boot\0" \
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"bootfile=zImage\0" \
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"fdtfile=da850-lcdk.dtb\0" \
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"boot_fdt=yes\0" \
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"boot_fit=0\0" \
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"console=ttyS2,115200n8\0"
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#ifdef CONFIG_CMD_BDI
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#define CONFIG_CLOCKS
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#endif
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/* SD/MMC */
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/* defines for SPL */
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#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
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CONFIG_SYS_MALLOC_LEN)
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#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
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#define CONFIG_SPL_STACK 0x8001ff00
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#define CONFIG_SPL_MAX_FOOTPRINT 32768
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#define CONFIG_SPL_PAD_TO 32768
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/* additions for new relocation code, must added to all boards */
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#define CONFIG_SYS_SDRAM_BASE 0xc0000000
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
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GENERATED_GBL_DATA_SIZE)
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#include <asm/arch/hardware.h>
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#endif /* __CONFIG_H */
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