mirror of
https://github.com/AsahiLinux/u-boot
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179 lines
5.2 KiB
ArmAsm
179 lines
5.2 KiB
ArmAsm
/*
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modified from SH-IPL+g
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Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
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Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
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Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/processor.h>
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#ifdef CONFIG_CPU_SH7751
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#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
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#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
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#ifdef CONFIG_MARUBUN_PCCARD
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#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
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A3:2 A2:15 A1:15 A0:6 A0B:7 */
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#else /* CONFIG_MARUBUN_PCCARD */
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#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
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A3:2 A2:15 A1:15 A0:6 A0B:7 */
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#endif /* CONFIG_MARUBUN_PCCARD */
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#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
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A2: 1-3 A1: 1-3 A0: 0-1 */
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#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
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#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
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#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */
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#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
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#else /* CONFIG_CPU_SH7751 */
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#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
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#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
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#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
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A3:2 A2:15 A1:15 A0:15 A0B:7 */
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#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
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A2: 1-3 A1: 1-3 A0: 0-1 */
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#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
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#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
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#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */
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#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
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#endif /* CONFIG_CPU_SH7751 */
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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mov.l CCR_A, r1 ! CCR Address
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mov.l CCR_D_DISABLE, r0 ! CCR Data
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mov.l r0, @r1
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init_bsc:
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mov.l FRQCR_A,r1 /* FRQCR Address */
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mov.l FRQCR_D,r0 /* FRQCR Data */
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mov.w r0,@r1
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mov.l BCR1_A,r1 /* BCR1 Address */
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mov.l BCR1_D,r0 /* BCR1 Data */
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mov.l r0,@r1
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mov.l BCR2_A,r1 /* BCR2 Address */
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mov.l BCR2_D,r0 /* BCR2 Data */
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mov.w r0,@r1
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mov.l WCR1_A,r1 /* WCR1 Address */
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mov.l WCR1_D,r0 /* WCR1 Data */
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mov.l r0,@r1
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mov.l WCR2_A,r1 /* WCR2 Address */
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mov.l WCR2_D,r0 /* WCR2 Data */
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mov.l r0,@r1
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mov.l WCR3_A,r1 /* WCR3 Address */
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mov.l WCR3_D,r0 /* WCR3 Data */
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mov.l r0,@r1
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mov.l MCR_A,r1 /* MCR Address */
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mov.l MCR_D1,r0 /* MCR Data1 */
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mov.l r0,@r1
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mov.l SDMR3_A,r1 /* Set SDRAM mode */
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mov #0,r0
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mov.b r0,@r1
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! Do you need PCMCIA setting?
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! If so, please add the lines here...
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mov.l RTCNT_A,r1 /* RTCNT Address */
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mov.l RTCNT_D,r0 /* RTCNT Data */
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mov.w r0,@r1
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mov.l RTCOR_A,r1 /* RTCOR Address */
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mov.l RTCOR_D,r0 /* RTCOR Data */
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mov.w r0,@r1
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mov.l RTCSR_A,r1 /* RTCSR Address */
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mov.l RTCSR_D,r0 /* RTCSR Data */
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mov.w r0,@r1
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mov.l RFCR_A,r1 /* RFCR Address */
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mov.l RFCR_D,r0 /* RFCR Data */
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mov.w r0,@r1 /* Clear reflesh counter */
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/* Wait DRAM refresh 30 times */
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mov #30,r3
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1:
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mov.w @r1,r0
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extu.w r0,r2
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cmp/hi r3,r2
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bf 1b
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mov.l MCR_A,r1 /* MCR Address */
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mov.l MCR_D2,r0 /* MCR Data2 */
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mov.l r0,@r1
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mov.l SDMR3_A,r1 /* Set SDRAM mode */
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mov #0,r0
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mov.b r0,@r1
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rts
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nop
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.align 2
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CCR_A: .long CCR
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CCR_D_DISABLE: .long 0x0808
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FRQCR_A: .long FRQCR
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FRQCR_D:
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#ifdef CONFIG_CPU_TYPE_R
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.long 0x00000e1a /* 12:3:3 */
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#else /* CONFIG_CPU_TYPE_R */
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#ifdef CONFIG_GOOD_SESH4
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.long 0x00000e13 /* 6:2:1 */
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#else
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.long 0x00000e23 /* 6:1:1 */
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#endif
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#endif /* CONFIG_CPU_TYPE_R */
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BCR1_A: .long BCR1
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BCR1_D: .long 0x00000008 /* Area 3 SDRAM */
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BCR2_A: .long BCR2
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BCR2_D: .long BCR2_D_VALUE /* Bus width settings */
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WCR1_A: .long WCR1
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WCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */
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WCR2_A: .long WCR2
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WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */
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WCR3_A: .long WCR3
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WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */
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RTCSR_A: .long RTCSR
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RTCSR_D: .long 0xA518 /* RTCSR Write Code A5h Data 18h */
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RTCNT_A: .long RTCNT
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RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */
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RTCOR_A: .long RTCOR
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RTCOR_D: .long RTCOR_D_VALUE /* Set refresh time (about 15us) */
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SDMR3_A: .long SDMR3_ADDRESS
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MCR_A: .long MCR
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MCR_D1: .long MCR_D1_VALUE
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MCR_D2: .long MCR_D2_VALUE
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RFCR_A: .long RFCR
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RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */
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