mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-05 20:54:31 +00:00
322 lines
7.3 KiB
C
322 lines
7.3 KiB
C
#include <common.h>
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#include <asm/io.h>
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#ifdef CONFIG_POST
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#include <post.h>
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#include <watchdog.h>
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#if CONFIG_POST & CFG_POST_MEMORY
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#define CLKIN 25000000
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#define PATTERN1 0x5A5A5A5A
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#define PATTERN2 0xAAAAAAAA
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#define CCLK_NUM 4
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#define SCLK_NUM 3
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void post_out_buff(char *buff);
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int post_key_pressed(void);
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void post_init_pll(int mult, int div);
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int post_init_sdram(int sclk);
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void post_init_uart(int sclk);
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const int pll[CCLK_NUM][SCLK_NUM][2] = {
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{{20, 4}, {20, 5}, {20, 10}}, /* CCLK = 500M */
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{{16, 4}, {16, 5}, {16, 8}}, /* CCLK = 400M */
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{{8, 2}, {8, 4}, {8, 5}}, /* CCLK = 200M */
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{{4, 1}, {4, 2}, {4, 4}} /* CCLK = 100M */
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};
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const char *const log[CCLK_NUM][SCLK_NUM] = {
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{"CCLK-500Mhz SCLK-125Mhz: Writing...\0",
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"CCLK-500Mhz SCLK-100Mhz: Writing...\0",
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"CCLK-500Mhz SCLK- 50Mhz: Writing...\0",},
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{"CCLK-400Mhz SCLK-100Mhz: Writing...\0",
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"CCLK-400Mhz SCLK- 80Mhz: Writing...\0",
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"CCLK-400Mhz SCLK- 50Mhz: Writing...\0",},
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{"CCLK-200Mhz SCLK-100Mhz: Writing...\0",
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"CCLK-200Mhz SCLK- 50Mhz: Writing...\0",
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"CCLK-200Mhz SCLK- 40Mhz: Writing...\0",},
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{"CCLK-100Mhz SCLK-100Mhz: Writing...\0",
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"CCLK-100Mhz SCLK- 50Mhz: Writing...\0",
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"CCLK-100Mhz SCLK- 25Mhz: Writing...\0",},
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};
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int memory_post_test(int flags)
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{
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int addr;
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int m, n;
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int sclk, sclk_temp;
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int ret = 1;
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sclk_temp = CLKIN / 1000000;
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sclk_temp = sclk_temp * CONFIG_VCO_MULT;
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for (sclk = 0; sclk_temp > 0; sclk++)
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sclk_temp -= CONFIG_SCLK_DIV;
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sclk = sclk * 1000000;
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post_init_uart(sclk);
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if (post_key_pressed() == 0)
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return 0;
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for (m = 0; m < CCLK_NUM; m++) {
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for (n = 0; n < SCLK_NUM; n++) {
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/* Calculate the sclk */
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sclk_temp = CLKIN / 1000000;
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sclk_temp = sclk_temp * pll[m][n][0];
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for (sclk = 0; sclk_temp > 0; sclk++)
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sclk_temp -= pll[m][n][1];
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sclk = sclk * 1000000;
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post_init_pll(pll[m][n][0], pll[m][n][1]);
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post_init_sdram(sclk);
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post_init_uart(sclk);
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post_out_buff("\n\r\0");
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post_out_buff(log[m][n]);
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for (addr = 0x0; addr < CFG_MAX_RAM_SIZE; addr += 4)
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*(unsigned long *)addr = PATTERN1;
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post_out_buff("Reading...\0");
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for (addr = 0x0; addr < CFG_MAX_RAM_SIZE; addr += 4) {
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if ((*(unsigned long *)addr) != PATTERN1) {
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post_out_buff("Error\n\r\0");
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ret = 0;
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}
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}
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post_out_buff("OK\n\r\0");
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}
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}
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if (ret)
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post_out_buff("memory POST passed\n\r\0");
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else
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post_out_buff("memory POST failed\n\r\0");
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post_out_buff("\n\r\n\r\0");
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return 1;
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}
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void post_init_uart(int sclk)
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{
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int divisor;
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for (divisor = 0; sclk > 0; divisor++)
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sclk -= 57600 * 16;
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*pPORTF_FER = 0x000F;
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*pPORTH_FER = 0xFFFF;
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*pUART_GCTL = 0x00;
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*pUART_LCR = 0x83;
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SSYNC();
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*pUART_DLL = (divisor & 0xFF);
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SSYNC();
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*pUART_DLH = ((divisor >> 8) & 0xFF);
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SSYNC();
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*pUART_LCR = 0x03;
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SSYNC();
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*pUART_GCTL = 0x01;
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SSYNC();
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}
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void post_out_buff(char *buff)
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{
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int i = 0;
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for (i = 0; i < 0x80000; i++) ;
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i = 0;
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while ((buff[i] != '\0') && (i != 100)) {
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while (!(*pUART_LSR & 0x20)) ;
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*pUART_THR = buff[i];
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SSYNC();
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i++;
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}
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for (i = 0; i < 0x80000; i++) ;
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}
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/* Using sw10-PF5 as the hotkey */
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#define KEY_LOOP 0x80000
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#define KEY_DELAY 0x80
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int post_key_pressed(void)
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{
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int i, n;
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unsigned short value;
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*pPORTF_FER &= ~PF5;
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*pPORTFIO_DIR &= ~PF5;
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*pPORTFIO_INEN |= PF5;
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SSYNC();
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post_out_buff("########Press SW10 to enter Memory POST########: 3\0");
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for (i = 0; i < KEY_LOOP; i++) {
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value = *pPORTFIO & PF5;
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if (*pUART0_RBR == 0x0D) {
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value = 0;
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goto key_pressed;
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}
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if (value != 0) {
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goto key_pressed;
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}
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for (n = 0; n < KEY_DELAY; n++)
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asm("nop");
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}
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post_out_buff("\b2\0");
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for (i = 0; i < KEY_LOOP; i++) {
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value = *pPORTFIO & PF5;
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if (*pUART0_RBR == 0x0D) {
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value = 0;
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goto key_pressed;
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}
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if (value != 0) {
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goto key_pressed;
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}
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for (n = 0; n < KEY_DELAY; n++)
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asm("nop");
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}
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post_out_buff("\b1\0");
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for (i = 0; i < KEY_LOOP; i++) {
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value = *pPORTFIO & PF5;
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if (*pUART0_RBR == 0x0D) {
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value = 0;
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goto key_pressed;
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}
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if (value != 0) {
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goto key_pressed;
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}
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for (n = 0; n < KEY_DELAY; n++)
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asm("nop");
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}
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key_pressed:
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post_out_buff("\b0");
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post_out_buff("\n\r\0");
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if (value == 0)
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return 0;
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post_out_buff("Hotkey has been pressed, Enter POST . . . . . .\n\r\0");
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return 1;
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}
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void post_init_pll(int mult, int div)
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{
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*pSIC_IWR = 0x01;
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*pPLL_CTL = (mult << 9);
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*pPLL_DIV = div;
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asm("CLI R2;");
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asm("IDLE;");
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asm("STI R2;");
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while (!(*pPLL_STAT & 0x20)) ;
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}
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int post_init_sdram(int sclk)
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{
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int SDRAM_tRP, SDRAM_tRP_num, SDRAM_tRAS, SDRAM_tRAS_num, SDRAM_tRCD,
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SDRAM_tWR;
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int SDRAM_Tref, SDRAM_NRA, SDRAM_CL, SDRAM_SIZE, SDRAM_WIDTH,
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mem_SDGCTL, mem_SDBCTL, mem_SDRRC;
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if ((sclk > 119402985)) {
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SDRAM_tRP = TRP_2;
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SDRAM_tRP_num = 2;
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SDRAM_tRAS = TRAS_7;
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SDRAM_tRAS_num = 7;
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SDRAM_tRCD = TRCD_2;
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SDRAM_tWR = TWR_2;
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} else if ((sclk > 104477612) && (sclk <= 119402985)) {
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SDRAM_tRP = TRP_2;
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SDRAM_tRP_num = 2;
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SDRAM_tRAS = TRAS_6;
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SDRAM_tRAS_num = 6;
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SDRAM_tRCD = TRCD_2;
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SDRAM_tWR = TWR_2;
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} else if ((sclk > 89552239) && (sclk <= 104477612)) {
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SDRAM_tRP = TRP_2;
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SDRAM_tRP_num = 2;
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SDRAM_tRAS = TRAS_5;
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SDRAM_tRAS_num = 5;
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SDRAM_tRCD = TRCD_2;
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SDRAM_tWR = TWR_2;
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} else if ((sclk > 74626866) && (sclk <= 89552239)) {
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SDRAM_tRP = TRP_2;
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SDRAM_tRP_num = 2;
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SDRAM_tRAS = TRAS_4;
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SDRAM_tRAS_num = 4;
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SDRAM_tRCD = TRCD_2;
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SDRAM_tWR = TWR_2;
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} else if ((sclk > 66666667) && (sclk <= 74626866)) {
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SDRAM_tRP = TRP_2;
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SDRAM_tRP_num = 2;
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SDRAM_tRAS = TRAS_3;
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SDRAM_tRAS_num = 3;
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SDRAM_tRCD = TRCD_2;
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SDRAM_tWR = TWR_2;
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} else if ((sclk > 59701493) && (sclk <= 66666667)) {
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SDRAM_tRP = TRP_1;
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SDRAM_tRP_num = 1;
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SDRAM_tRAS = TRAS_4;
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SDRAM_tRAS_num = 4;
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SDRAM_tRCD = TRCD_1;
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SDRAM_tWR = TWR_2;
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} else if ((sclk > 44776119) && (sclk <= 59701493)) {
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SDRAM_tRP = TRP_1;
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SDRAM_tRP_num = 1;
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SDRAM_tRAS = TRAS_3;
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SDRAM_tRAS_num = 3;
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SDRAM_tRCD = TRCD_1;
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SDRAM_tWR = TWR_2;
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} else if ((sclk > 29850746) && (sclk <= 44776119)) {
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SDRAM_tRP = TRP_1;
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SDRAM_tRP_num = 1;
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SDRAM_tRAS = TRAS_2;
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SDRAM_tRAS_num = 2;
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SDRAM_tRCD = TRCD_1;
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SDRAM_tWR = TWR_2;
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} else if (sclk <= 29850746) {
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SDRAM_tRP = TRP_1;
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SDRAM_tRP_num = 1;
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SDRAM_tRAS = TRAS_1;
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SDRAM_tRAS_num = 1;
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SDRAM_tRCD = TRCD_1;
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SDRAM_tWR = TWR_2;
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} else {
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SDRAM_tRP = TRP_1;
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SDRAM_tRP_num = 1;
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SDRAM_tRAS = TRAS_1;
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SDRAM_tRAS_num = 1;
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SDRAM_tRCD = TRCD_1;
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SDRAM_tWR = TWR_2;
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}
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/*SDRAM INFORMATION: */
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SDRAM_Tref = 64; /* Refresh period in milliseconds */
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SDRAM_NRA = 4096; /* Number of row addresses in SDRAM */
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SDRAM_CL = CL_3; /* 2 */
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SDRAM_SIZE = EBSZ_64;
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SDRAM_WIDTH = EBCAW_10;
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mem_SDBCTL = SDRAM_WIDTH | SDRAM_SIZE | EBE;
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/* Equation from section 17 (p17-46) of BF533 HRM */
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mem_SDRRC =
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(((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) -
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(SDRAM_tRAS_num + SDRAM_tRP_num);
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/* Enable SCLK Out */
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mem_SDGCTL =
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(SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR
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| PSS);
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SSYNC();
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*pEBIU_SDGCTL |= 0x1000000;
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/* Set the SDRAM Refresh Rate control register based on SSCLK value */
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*pEBIU_SDRRC = mem_SDRRC;
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/* SDRAM Memory Bank Control Register */
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*pEBIU_SDBCTL = mem_SDBCTL;
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/* SDRAM Memory Global Control Register */
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*pEBIU_SDGCTL = mem_SDGCTL;
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SSYNC();
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return mem_SDRRC;
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}
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#endif /* CONFIG_POST & CFG_POST_MEMORY */
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#endif /* CONFIG_POST */
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