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19ed7b4ecf
Tegra's "APB misc" register region contains various miscellaneous registers and the Tegra pinmux registers. Some code that touches the misc registers currently uses struct pmux_tri_ctlr, which is intended to be a definition of pinmux registers, rather than struct apb_misc_pp_ctrl, which is intended to be a definition of the miscellaneous registers. Convert all such code to use struct apb_misc_pp_ctrl, since struct pmux_tri_ctlr goes away in the next patch. This requires adding a missing field definition to struct apb_misc_pp_ctrl, and moving the header into a more common location. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
22 lines
494 B
C
22 lines
494 B
C
/*
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* Copyright (c) 2012 The Chromium OS Authors.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _GP_PADCTRL_H_
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#define _GP_PADCTRL_H_
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/* APB_MISC_PP registers */
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struct apb_misc_pp_ctlr {
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u32 reserved0[2];
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u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */
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u32 reserved1[6]; /* 0x0c .. 0x20 */
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u32 cfg_ctl; /* 0x24 */
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};
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/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */
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#define RAM_CODE_SHIFT 4
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#define RAM_CODE_MASK (0xf << RAM_CODE_SHIFT)
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#endif
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