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a4954f9467
LS2080a, LS1088a and LS2088a SOCs are based on Chassis-3 and shared same stream-id partitioning. This patch rewords the definition to support all these SOCs. Also have changes in description about iommu-map property updates in PCI node. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
80 lines
3 KiB
C
80 lines
3 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*/
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#ifndef __FSL_STREAM_ID_H
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#define __FSL_STREAM_ID_H
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/*
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* Stream IDs on NXP Chassis-3 (for example ls2080a, ls1088a, ls2088a)
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* devices are not hardwired and are programmed by sw. There are a limited
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* number of stream IDs available, and the partitioning of them is scenario
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* dependent. This header defines the partitioning between legacy,
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* PCI, and DPAA2 devices.
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*
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* This partitioning can be customized in this file depending
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* on the specific hardware config:
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*
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* -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
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* -all legacy devices get a unique stream ID assigned and programmed in
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* their AMQR registers by u-boot
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*
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* -PCIe
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* -there is a range of stream IDs set aside for PCI in this
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* file. U-boot will scan the PCI bus and for each device discovered:
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* -allocate a streamID
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* -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
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* -set a msi-map entry in the PEXn controller node in the
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* device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
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* for more info on the msi-map definition)
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* -set a iommu-map entry in the PEXn controller node in the
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* device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt
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* for more info on the iommu-map definition)
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*
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* -DPAA2
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* -u-boot will allocate a range of stream IDs to be used by the Management
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* Complex for containers and will set these values in the MC DPC image.
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* -the MC is responsible for allocating and setting up 'isolation context
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* IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
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*
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* On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for
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* each of the different bus masters. The relationship between
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* the AMQ registers and stream IDs is defined in the table below:
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* AMQ bit streamID bit
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* ---------------------------
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* PL[18] 9 // privilege bit
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* BMT[17] 8 // bypass translation
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* VA[16] 7 // reserved
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* [15] - // unused
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* ICID[14:7] - // unused
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* ICID[6:0] 6-0 // isolation context id
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* ----------------------------
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*
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*/
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#define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */
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#define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */
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#define FSL_INVALID_STREAM_ID 0
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#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK)
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/* legacy devices */
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#define FSL_USB1_STREAM_ID 1
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#define FSL_USB2_STREAM_ID 2
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#define FSL_SDMMC_STREAM_ID 3
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#define FSL_SATA1_STREAM_ID 4
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#define FSL_SATA2_STREAM_ID 5
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#define FSL_DMA_STREAM_ID 6
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/* PCI - programmed in PEXn_LUT */
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#define FSL_PEX_STREAM_ID_START 7
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#define FSL_PEX_STREAM_ID_END 22
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/* DPAA2 - set in MC DPC and alloced by MC */
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#define FSL_DPAA2_STREAM_ID_START 23
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#define FSL_DPAA2_STREAM_ID_END 63
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#endif
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