Chris Morgan 95ef2aaedc rockchip: rk3568: enable automatic power savings ... It enables automatic clock gating on idle, disables the eDP phy by default, and sets the core pvtpll ring length. It is reported this lowers the temperature on at least one SoC by 7C. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>		2023-02-28 18:07:27 +08:00
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clk_rk3568.c	rockchip: Add rk3568 architecture core	2021-06-18 14:36:24 +08:00
Kconfig	rockchip: move ROCKCHIP_STIMER_BASE to Kconfig	2022-04-18 11:25:12 +08:00
Makefile	rockchip: Add rk3568 architecture core	2021-06-18 14:36:24 +08:00
rk3568.c	rockchip: rk3568: enable automatic power savings	2023-02-28 18:07:27 +08:00
syscon_rk3568.c	treewide: Use OF_REAL instead of !OF_PLATDATA	2021-09-25 09:46:15 -06:00