mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-22 03:03:05 +00:00
4e2e2f8984
Add gpio pins present on new board revision: * LTE modem support (imx8mm-gw7902 only) - lte_pwr# - lte_rst - lte_int * M2 power enable - m2_pwr_en * off-board 4.0V supply - vdd_4p0_en Signed-off-by: Tim Harvey <tharvey@gateworks.com>
150 lines
2.1 KiB
Text
150 lines
2.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 Gateworks Corporation
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*/
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#include "imx8mn-venice-u-boot.dtsi"
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&gpio1 {
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m2pwren {
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gpio-hog;
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output-low;
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gpios = <8 GPIO_ACTIVE_HIGH>;
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line-name = "m2_pwren";
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};
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m2rst {
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gpio-hog;
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output-low;
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gpios = <13 GPIO_ACTIVE_HIGH>;
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line-name = "m2_reset";
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};
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m2wdis {
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gpio-hog;
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output-high;
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gpios = <15 GPIO_ACTIVE_HIGH>;
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line-name = "m2_wdis#";
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};
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};
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&gpio2 {
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uart2en {
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gpio-hog;
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output-high;
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gpios = <8 GPIO_ACTIVE_HIGH>;
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line-name = "uart2_en#";
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};
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};
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&gpio3 {
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m2gdis {
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gpio-hog;
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output-high;
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gpios = <1 GPIO_ACTIVE_HIGH>;
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line-name = "m2_gdis#";
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};
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m2off {
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gpio-hog;
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output-high;
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gpios = <7 GPIO_ACTIVE_HIGH>;
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line-name = "m2_off#";
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};
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};
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&gpio4 {
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appgpio1 {
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gpio-hog;
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input;
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gpios = <21 GPIO_ACTIVE_HIGH>;
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line-name = "app_gpio1";
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};
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vdd4p0en {
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gpio-hog;
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output-low;
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gpios = <22 GPIO_ACTIVE_HIGH>;
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line-name = "vdd_4p0_en";
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};
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uart1rs485 {
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gpio-hog;
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output-low;
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gpios = <23 GPIO_ACTIVE_HIGH>;
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line-name = "uart1_rs485";
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};
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uart1term {
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gpio-hog;
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output-low;
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gpios = <25 GPIO_ACTIVE_HIGH>;
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line-name = "uart1_term";
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};
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uart1half {
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gpio-hog;
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output-low;
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gpios = <26 GPIO_ACTIVE_HIGH>;
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line-name = "uart1_half";
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};
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appgpio2 {
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gpio-hog;
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input;
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gpios = <27 GPIO_ACTIVE_HIGH>;
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line-name = "app_gpio2";
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};
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mipigpio1 {
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gpio-hog;
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input;
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gpios = <28 GPIO_ACTIVE_HIGH>;
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line-name = "mipi_gpio1";
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};
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};
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&gpio5 {
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mipigpio4 {
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gpio-hog;
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input;
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gpios = <3 GPIO_ACTIVE_HIGH>;
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line-name = "mipi_gpio4";
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};
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mipigpio3 {
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gpio-hog;
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input;
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gpios = <4 GPIO_ACTIVE_HIGH>;
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line-name = "mipi_gpio3";
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};
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mipigpio2 {
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gpio-hog;
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input;
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gpios = <5 GPIO_ACTIVE_HIGH>;
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line-name = "mipi_gpio2";
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};
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};
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&fec1 {
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phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <1>;
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phy-reset-post-delay = <300>;
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};
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&pinctrl_fec1 {
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u-boot,dm-spl;
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};
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&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
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u-boot,dm-spl;
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};
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&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
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u-boot,dm-spl;
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};
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&pinctrl_pmic {
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u-boot,dm-spl;
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};
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