mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-19 01:33:10 +00:00
2395625209
The GW74xx is based on the i.MX 8M Plus SoC featuring:
- LPDDR4 DRAM
- eMMC FLASH
- Gateworks System Controller
- PCIe Gen 3.0 switch (build option)
- USB 3.0 HUB
- USB Type-C front panel connector
- GPS
- 3-axis accelerometer
- CAN bus
- 6x GbE RJ45 front-panel jacks
- 1x IMX8M FEC RGMII GbE (with Passive PoE)
- 5x IMX8M EQOS RGMII 6 port GbE Switch
(1x with 802.3af class 5 Active PoE)
- RS232/RS485/RS422 serial transceiver
- MIPI header (DSI/CSI/GPIO/PWM/I2S)
- DigI/O header (UART/GPIO/I2C/ADC)
- 802.11ac WiFi
- Bluetooth BLE
- 3x MiniPCIe sockets with PCI/USB
- 1x M.2 Socket with USB2.0, PCIe, and dual-SIM
- PMIC
- Wide range DC input supply (8V to 60V DC)
Do the following to add support for this and future imx8mp-venice boards:
- add dts
- add DRAM config
- add PMIC config
- add IMX8MP support in spl.c and venice.c
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
22 lines
673 B
C
22 lines
673 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* Copyright 2021 Gateworks Corporation
|
|
*/
|
|
|
|
#ifndef __LPDDR4_TIMING_H__
|
|
#define __LPDDR4_TIMING_H__
|
|
|
|
#ifdef CONFIG_IMX8MM
|
|
extern struct dram_timing_info dram_timing_512mb;
|
|
extern struct dram_timing_info dram_timing_1gb;
|
|
extern struct dram_timing_info dram_timing_2gb;
|
|
extern struct dram_timing_info dram_timing_4gb;
|
|
#elif CONFIG_IMX8MN
|
|
extern struct dram_timing_info dram_timing_1gb_single_die;
|
|
extern struct dram_timing_info dram_timing_2gb_single_die;
|
|
extern struct dram_timing_info dram_timing_2gb_dual_die;
|
|
#elif CONFIG_IMX8MP
|
|
extern struct dram_timing_info dram_timing_4gb_dual_die;
|
|
#endif
|
|
|
|
#endif /* __LPDDR4_TIMING_H__ */
|