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158097052a
Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
19 lines
397 B
C
19 lines
397 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*/
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#ifndef __FSL_LS102XA_SOC_H
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#define __FSL_LS102XA_SOC_H
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unsigned int get_soc_major_rev(void);
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int arch_soc_init(void);
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int ls102xa_smmu_stream_id_init(void);
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void erratum_a008850_post(void);
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#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
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void erratum_a010315(void);
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#endif
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#endif /* __FSL_LS102XA_SOC_H */
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