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AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
38 lines
872 B
C
38 lines
872 B
C
/*
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* clocks_am33xx.h
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*
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* AM33xx clock define
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CLOCKS_AM33XX_H_
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#define _CLOCKS_AM33XX_H_
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/* MAIN PLL Fdll supported frequencies */
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#define MPUPLL_M_1000 1000
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#define MPUPLL_M_800 800
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#define MPUPLL_M_720 720
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#define MPUPLL_M_600 600
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#define MPUPLL_M_550 550
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#define MPUPLL_M_300 300
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/* MAIN PLL Fdll = 550 MHz, by default */
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#ifndef CONFIG_SYS_MPUCLK
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#define CONFIG_SYS_MPUCLK MPUPLL_M_550
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#endif
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#define UART_RESET (0x1 << 1)
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#define UART_CLK_RUNNING_MASK 0x1
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#define UART_SMART_IDLE_EN (0x1 << 0x3)
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#define CM_DLL_CTRL_NO_OVERRIDE 0x0
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#define CM_DLL_READYST 0x4
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extern void enable_dmm_clocks(void);
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extern const struct dpll_params dpll_core_opp100;
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extern struct dpll_params dpll_mpu_opp100;
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#endif /* endif _CLOCKS_AM33XX_H_ */
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