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1d3d0f1f1c
This patch add some common code for QCA/Atheros ath79 SOCs such as DDR tuning, chip reset and CPU detection. Signed-off-by: Wills Wang <wills.wang@live.com>
38 lines
836 B
C
38 lines
836 B
C
/*
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* (C) Copyright 2002-2010
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_GBL_DATA_H
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#define __ASM_GBL_DATA_H
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#include <asm/regdef.h>
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/* Architecture-specific global data */
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struct arch_global_data {
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#ifdef CONFIG_DYNAMIC_IO_PORT_BASE
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unsigned long io_port_base;
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#endif
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#ifdef CONFIG_JZSOC
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/* There are other clocks in the jz4740 */
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unsigned long per_clk; /* Peripheral bus clock */
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unsigned long dev_clk; /* Device clock */
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unsigned long sys_clk;
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unsigned long tbl;
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unsigned long lastinc;
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#endif
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#ifdef CONFIG_ARCH_ATH79
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unsigned long id;
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unsigned long soc;
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unsigned long rev;
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unsigned long ver;
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#endif
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};
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#include <asm-generic/global_data.h>
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#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("k0")
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#endif /* __ASM_GBL_DATA_H */
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