mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-30 16:39:35 +00:00
8bde7f776c
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
766 lines
20 KiB
C
766 lines
20 KiB
C
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* Keith Outwater, keith_outwater@mvis.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config_GEN860T.h - board specific configuration options
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*/
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#ifndef __CONFIG_GEN860T_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_MPC860
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#define CONFIG_GEN860T
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/*
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* Identify the board
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*/
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#if !defined(CONFIG_SC)
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#define CONFIG_IDENT_STRING " B2"
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#else
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#define CONFIG_IDENT_STRING " SC"
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#endif
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/*
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* Don't depend on the RTC clock to determine clock frequency -
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* the 860's internal rtc uses a 32.768 KHz clock which is
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* generated by the DS1337 - and the DS1337 clock can be turned off.
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*/
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#if !defined(CONFIG_SC)
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#define CONFIG_8xx_GCLK_FREQ 66600000
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#else
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#define CONFIG_8xx_GCLK_FREQ 48000000
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#endif
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/*
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* The RS-232 console port is on SMC1
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*/
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#define CONFIG_8xx_CONS_SMC1
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#define CONFIG_BAUDRATE 38400
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/*
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* Set allowable console baud rates
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*/
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#define CFG_BAUDRATE_TABLE { 9600, \
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19200, \
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38400, \
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57600, \
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115200, \
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}
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/*
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* Print console information
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*/
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#undef CFG_CONSOLE_INFO_QUIET
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/*
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* Set the autoboot delay in seconds. A delay of -1 disables autoboot
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*/
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#define CONFIG_BOOTDELAY 5
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/*
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* Pass the clock frequency to the Linux kernel in units of MHz
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*/
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#define CONFIG_CLOCKS_IN_MHZ
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#define CONFIG_PREBOOT \
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"echo;echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"bootp;" \
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"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
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"bootm"
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/*
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* Turn off echo for serial download by default. Allow baud rate to be changed
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* for downloads
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*/
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#undef CONFIG_LOADS_ECHO
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#define CFG_LOADS_BAUD_CHANGE
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/*
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* Set default load address for tftp network downloads
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*/
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#define CFG_TFTP_LOADADDR 0x01000000
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/*
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* Turn off the watchdog timer
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*/
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#undef CONFIG_WATCHDOG
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/*
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* Do not reboot if a panic occurs
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*/
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#define CONFIG_PANIC_HANG
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/*
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* Enable the status LED
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*/
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#define CONFIG_STATUS_LED
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/*
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* Reset address. We pick an address such that when an instruction
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* is executed at that address, a machine check exception occurs
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*/
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#define CFG_RESET_ADDRESS ((ulong) -1)
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \
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CONFIG_BOOTP_BOOTFILESIZE \
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)
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/*
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* The GEN860T network interface uses the on-chip 10/100 FEC with
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* an Intel LXT971A PHY connected to the 860T's MII. The PHY's
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* MII address is hardwired on the board to zero.
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*/
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#define CONFIG_FEC_ENET
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#define CFG_DISCOVER_PHY
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#define CONFIG_MII
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#define CONFIG_PHY_ADDR 0
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/*
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* Set default IP stuff just to get bootstrap entries into the
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* environment so that we can autoscript the full default environment.
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*/
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#define CONFIG_ETHADDR 9a:52:63:15:85:25
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#define CONFIG_SERVERIP 10.0.4.201
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#define CONFIG_IPADDR 10.0.4.111
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/*
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* This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
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* the MPC860T I2C interface.
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*/
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#define CFG_I2C_EEPROM_ADDR 0x50
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#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10 mS w/ 20% margin */
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#define CFG_I2C_EEPROM_ADDR_LEN 2 /* need 16 bit address */
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#define CFG_ENV_EEPROM_SIZE (32 * 1024)
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/*
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* Enable I2C and select the hardware/software driver
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*/
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#define CONFIG_HARD_I2C 1 /* CPM based I2C */
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#undef CONFIG_SOFT_I2C /* Bit-banged I2C */
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#ifdef CONFIG_HARD_I2C
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#define CFG_I2C_SPEED 100000 /* clock speed in Hz */
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#define CFG_I2C_SLAVE 0xFE /* I2C slave address */
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#endif
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#ifdef CONFIG_SOFT_I2C
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#define PB_SCL 0x00000020 /* PB 26 */
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#define PB_SDA 0x00000010 /* PB 27 */
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#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
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#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
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#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
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#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
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#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
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else immr->im_cpm.cp_pbdat &= ~PB_SDA
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#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
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else immr->im_cpm.cp_pbdat &= ~PB_SCL
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#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
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#endif
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/*
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* Allow environment overwrites by anyone
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*/
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#define CONFIG_ENV_OVERWRITE
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#if !defined(CONFIG_SC)
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/*
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* The MPC860's internal RTC is horribly broken in rev D masks. Three
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* internal MPC860T circuit nodes were inadvertently left floating; this
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* causes KAPWR current in power down mode to be three orders of magnitude
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* higher than specified in the datasheet (from 10 uA to 10 mA). No
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* reasonable battery can keep that kind RTC running during powerdown for any
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* length of time, so we use an external RTC on the I2C bus instead.
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*/
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#define CONFIG_RTC_DS1337
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#define CFG_I2C_RTC_ADDR 0x68
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#else
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/*
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* No external RTC on SC variant, so we're stuck with the internal one.
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*/
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#define CONFIG_RTC_MPC8xx
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#endif
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/*
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* Power On Self Test support
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*/
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#define CONFIG_POST ( CFG_POST_CACHE | \
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CFG_POST_MEMORY | \
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CFG_POST_CPU | \
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CFG_POST_UART | \
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CFG_POST_SPR )
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#ifdef CONFIG_POST
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#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
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#else
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#define CFG_CMD_POST_DIAG 0
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#endif
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/*
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* List of available monitor commands. Use the system default list
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* plus add some of the "non-standard" commands back in.
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* See ./cmd_confdefs.h
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*/
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#define BASE_CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_ASKENV | \
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CFG_CMD_DHCP | \
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CFG_CMD_I2C | \
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CFG_CMD_EEPROM | \
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CFG_CMD_REGINFO | \
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CFG_CMD_IMMAP | \
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CFG_CMD_ELF | \
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CFG_CMD_DATE | \
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CFG_CMD_FPGA | \
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CFG_CMD_MII | \
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CFG_CMD_BEDBUG | \
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CFG_CMD_POST_DIAG )
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#if !defined(CONFIG_SC)
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#define CONFIG_COMMANDS ( BASE_CONFIG_COMMANDS | CFG_CMD_DOC )
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#else
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#define CONFIG_COMMANDS BASE_CONFIG_COMMANDS
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#endif
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/*
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* There is no IDE/PCMCIA hardware support on the board.
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*/
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#undef CONFIG_IDE_PCMCIA
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#undef CONFIG_IDE_LED
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#undef CONFIG_IDE_RESET
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/*
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* Enable the call to misc_init_r() for miscellaneous platform
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* dependent initialization.
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*/
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#define CONFIG_MISC_INIT_R
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/*
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* Enable call to last_stage_init() so we can twiddle some LEDS :)
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*/
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#define CONFIG_LAST_STAGE_INIT
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/*
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* Virtex2 FPGA configuration support
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*/
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#define CONFIG_FPGA_COUNT 1
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#define CONFIG_FPGA CFG_XILINX_VIRTEX2
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#define CFG_FPGA_PROG_FEEDBACK
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/************************************************************************
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* This must be included AFTER the definition of any CONFIG_COMMANDS
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*/
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#include <cmd_confdefs.h>
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/*
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* Verbose help from command monitor.
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*/
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#define CFG_LONGHELP
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#if !defined(CONFIG_SC)
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#define CFG_PROMPT "B2> "
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#else
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#define CFG_PROMPT "SC> "
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#endif
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/*
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* Use the "hush" command parser
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*/
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#define CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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/*
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* Set buffer size for console I/O
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*/
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024
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#else
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#define CFG_CBSIZE 256
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#endif
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/*
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* Print buffer size
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*/
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#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
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/*
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* Maximum number of arguments that a command can accept
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*/
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#define CFG_MAXARGS 16
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/*
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* Boot argument buffer size
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*/
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#define CFG_BARGSIZE CFG_CBSIZE
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/*
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* Default memory test range
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*/
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#define CFG_MEMTEST_START 0x0100000
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#define CFG_MEMTEST_END (CFG_MEMTEST_START + (128 * 1024))
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/*
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* Select the more full-featured memory test
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*/
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#define CFG_ALT_MEMTEST
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/*
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* Default load address
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*/
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#define CFG_LOAD_ADDR 0x01000000
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/*
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* Set decrementer frequency (1 ms ticks)
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*/
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#define CFG_HZ 1000
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/*
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* Device memory map (after SDRAM remap to 0x0):
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*
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* CS Device Base Addr Size
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* ----------------------------------------------------
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* CS0* Flash 0x40000000 64 M
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* CS1* SDRAM 0x00000000 16 M
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* CS2* Disk-On-Chip 0x50000000 32 K
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* CS3* FPGA 0x60000000 64 M
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* CS4* SelectMap 0x70000000 32 K
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* CS5* Mil-Std 1553 I/F 0x80000000 32 K
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* CS6* Unused
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* CS7* Unused
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* IMMR 860T Registers 0xfff00000
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*/
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/*
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* Base addresses and block sizes
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*/
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#define CFG_IMMR 0xFF000000
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#define SDRAM_BASE 0x00000000
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#define SDRAM_SIZE (64 * 1024 * 1024)
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#define FLASH_BASE 0x40000000
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#define FLASH_SIZE (16 * 1024 * 1024)
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#define DOC_BASE 0x50000000
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#define DOC_SIZE (32 * 1024)
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#define FPGA_BASE 0x60000000
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#define FPGA_SIZE (64 * 1024 * 1024)
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#define SELECTMAP_BASE 0x70000000
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#define SELECTMAP_SIZE (32 * 1024)
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#define M1553_BASE 0x80000000
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#define M1553_SIZE (64 * 1024)
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/*
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE SDRAM_BASE
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/*
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* FLASH organization
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*/
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#define CFG_FLASH_BASE FLASH_BASE
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#define CFG_FLASH_SIZE FLASH_SIZE
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#define CFG_FLASH_SECT_SIZE (128 * 1024)
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#define CFG_MAX_FLASH_BANKS 1
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#define CFG_MAX_FLASH_SECT 128
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/*
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* The timeout values are for an entire chip and are in milliseconds.
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* Yes I know that the write timeout is huge. Accroding to the
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* datasheet a single byte takes 630 uS (round to 1 ms) max at worst
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* case VCC and temp after 100K programming cycles. It works out
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* to 280 minutes (might as well be forever).
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*/
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#define CFG_FLASH_ERASE_TOUT (CFG_MAX_FLASH_SECT * 5000)
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#define CFG_FLASH_WRITE_TOUT (CFG_MAX_FLASH_SECT * 128 * 1024 * 1)
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/*
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* Allow direct writes to FLASH from tftp transfers (** dangerous **)
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*/
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#define CFG_DIRECT_FLASH_TFTP
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/*
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* Reserve memory for U-Boot.
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*/
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#define CFG_MAX_UBOOT_SECTS 4
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#define CFG_MONITOR_LEN (CFG_MAX_UBOOT_SECTS * CFG_FLASH_SECT_SIZE)
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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/*
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* Select environment placement. NOTE that u-boot.lds must
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* be edited if this is changed!
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*/
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#undef CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_IS_IN_EEPROM
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#if defined(CFG_ENV_IS_IN_EEPROM)
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#define CFG_ENV_SIZE (2 * 1024)
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#define CFG_ENV_OFFSET (CFG_ENV_EEPROM_SIZE - (8 * 1024))
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#else
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#define CFG_ENV_SIZE 0x1000
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#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SIZE
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|
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/*
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* This ultimately gets passed right into the linker script, so we have to
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* use a number :(
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*/
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#define CFG_ENV_OFFSET 0x060000
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#endif
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/*
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* Reserve memory for malloc()
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*/
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#define CFG_MALLOC_LEN (128 * 1024)
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|
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
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|
|
/*
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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|
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of above value */
|
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#endif
|
|
|
|
/*------------------------------------------------------------------------
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|
* SYPCR - System Protection Control UM 11-9
|
|
* -----------------------------------------------------------------------
|
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* SYPCR can only be written once after reset!
|
|
*
|
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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|
*/
|
|
#if defined(CONFIG_WATCHDOG)
|
|
#define CFG_SYPCR ( SYPCR_SWTC | \
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SYPCR_BMT | \
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SYPCR_BME | \
|
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SYPCR_SWF | \
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SYPCR_SWE | \
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SYPCR_SWRI | \
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SYPCR_SWP \
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)
|
|
#else
|
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#define CFG_SYPCR ( SYPCR_SWTC | \
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SYPCR_BMT | \
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SYPCR_BME | \
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SYPCR_SWF | \
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SYPCR_SWP \
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)
|
|
#endif
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* SIUMCR - SIU Module Configuration UM 11-6
|
|
*-----------------------------------------------------------------------
|
|
* Set debug pin mux, enable SPKROUT and GPLB5*.
|
|
*/
|
|
#define CFG_SIUMCR ( SIUMCR_DBGC11 | \
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SIUMCR_DBPC11 | \
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SIUMCR_MLRC11 | \
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SIUMCR_GB5E \
|
|
)
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* TBSCR - Time Base Status and Control UM 11-26
|
|
*-----------------------------------------------------------------------
|
|
* Clear Reference Interrupt Status, Timebase freeze enabled
|
|
*/
|
|
#define CFG_TBSCR ( TBSCR_REFA | \
|
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TBSCR_REFB | \
|
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TBSCR_TBF \
|
|
)
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* RTCSC - Real-Time Clock Status and Control Register UM 11-27
|
|
*-----------------------------------------------------------------------
|
|
*/
|
|
#define CFG_RTCSC ( RTCSC_SEC | \
|
|
RTCSC_ALR | \
|
|
RTCSC_RTF | \
|
|
RTCSC_RTE \
|
|
)
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* PISCR - Periodic Interrupt Status and Control UM 11-31
|
|
*-----------------------------------------------------------------------
|
|
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
|
*/
|
|
#define CFG_PISCR ( PISCR_PS | \
|
|
PISCR_PITF \
|
|
)
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* PLPRCR - PLL, Low-Power, and Reset Control Register UM 15-30
|
|
*-----------------------------------------------------------------------
|
|
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
|
* interrupt status bit. Set MF for 1:2:1 mode.
|
|
*/
|
|
#define CFG_PLPRCR ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK) | \
|
|
PLPRCR_SPLSS | \
|
|
PLPRCR_TEXPS | \
|
|
PLPRCR_TMIST \
|
|
)
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* SCCR - System Clock and reset Control Register UM 15-27
|
|
*-----------------------------------------------------------------------
|
|
* Set clock output, timebase and RTC source and divider,
|
|
* power management and some other internal clocks
|
|
*/
|
|
#define SCCR_MASK SCCR_EBDF11
|
|
|
|
#if !defined(CONFIG_SC)
|
|
#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
|
|
SCCR_COM00 | /* full strength CLKOUT */ \
|
|
SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
|
|
SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
|
|
SCCR_DFNL000 | \
|
|
SCCR_DFNH000 \
|
|
)
|
|
#else
|
|
#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
|
|
SCCR_COM00 | /* full strength CLKOUT */ \
|
|
SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
|
|
SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
|
|
SCCR_DFNL000 | \
|
|
SCCR_DFNH000 | \
|
|
SCCR_RTDIV | \
|
|
SCCR_RTSEL \
|
|
)
|
|
#endif
|
|
|
|
/*-----------------------------------------------------------------------
|
|
* DER - Debug Enable Register UM 37-46
|
|
*-----------------------------------------------------------------------
|
|
* Mask all events that can cause entry into debug mode
|
|
*/
|
|
#define CFG_DER 0
|
|
|
|
/*
|
|
* Initialize Memory Controller:
|
|
*
|
|
* BR0 and OR0 (FLASH memory)
|
|
*/
|
|
#define FLASH_BASE0_PRELIM FLASH_BASE
|
|
|
|
/*
|
|
* Flash address mask
|
|
*/
|
|
#define CFG_PRELIM_OR_AM 0xfe000000
|
|
|
|
/*
|
|
* FLASH timing:
|
|
* 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
|
|
*/
|
|
#define CFG_OR_TIMING_FLASH ( OR_CSNT_SAM | \
|
|
OR_ACS_DIV2 | \
|
|
OR_BI | \
|
|
OR_SCY_2_CLK | \
|
|
OR_TRLX | \
|
|
OR_EHTR \
|
|
)
|
|
|
|
#define CFG_OR0_PRELIM ( CFG_PRELIM_OR_AM | \
|
|
CFG_OR_TIMING_FLASH \
|
|
)
|
|
|
|
#define CFG_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \
|
|
BR_MS_GPCM | \
|
|
BR_PS_8 | \
|
|
BR_V \
|
|
)
|
|
|
|
/*
|
|
* SDRAM configuration
|
|
*/
|
|
#define CFG_OR1_AM 0xfc000000
|
|
#define CFG_OR1 ( (CFG_OR1_AM & OR_AM_MSK) | \
|
|
OR_CSNT_SAM \
|
|
)
|
|
|
|
#define CFG_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \
|
|
BR_MS_UPMA | \
|
|
BR_PS_32 | \
|
|
BR_V \
|
|
)
|
|
|
|
/*
|
|
* Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
|
|
* of 256 MBit SDRAM
|
|
*/
|
|
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16
|
|
|
|
/*
|
|
* Periodic timer for refresh @ 33 MHz system clock
|
|
*/
|
|
#define CFG_MAMR_PTA 64
|
|
|
|
/*
|
|
* MAMR settings for SDRAM
|
|
*/
|
|
#define CFG_MAMR_8COL ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \
|
|
MAMR_PTAE | \
|
|
MAMR_AMA_TYPE_1 | \
|
|
MAMR_DSA_1_CYCL | \
|
|
MAMR_G0CLA_A10 | \
|
|
MAMR_RLFA_1X | \
|
|
MAMR_WLFA_1X | \
|
|
MAMR_TLFA_4X \
|
|
)
|
|
|
|
/*
|
|
* CS2* configuration for Disk On Chip:
|
|
* 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
|
|
* no burst.
|
|
*/
|
|
#define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
|
|
OR_CSNT_SAM | \
|
|
OR_ACS_DIV2 | \
|
|
OR_BI | \
|
|
OR_SCY_2_CLK | \
|
|
OR_TRLX | \
|
|
OR_EHTR \
|
|
)
|
|
|
|
#define CFG_BR2_PRELIM ( (DOC_BASE & BR_BA_MSK) | \
|
|
BR_PS_8 | \
|
|
BR_MS_GPCM | \
|
|
BR_V \
|
|
)
|
|
|
|
/*
|
|
* CS3* configuration for FPGA:
|
|
* 33 MHz bus with SCY=15, no burst.
|
|
* The FPGA uses TA and TEA to terminate bus cycles, but we
|
|
* clear SETA and set the cycle length to a large number so that
|
|
* the cycle will still complete even if there is a configuration
|
|
* error that prevents TA from asserting on FPGA accesss.
|
|
*/
|
|
#define CFG_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \
|
|
OR_SCY_15_CLK | \
|
|
OR_BI \
|
|
)
|
|
|
|
#define CFG_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \
|
|
BR_PS_32 | \
|
|
BR_MS_GPCM | \
|
|
BR_V \
|
|
)
|
|
/*
|
|
* CS4* configuration for FPGA SelectMap configuration interface.
|
|
* 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
|
|
* of GCLK1_50
|
|
*/
|
|
#define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
|
|
OR_G5LS | \
|
|
OR_BI \
|
|
)
|
|
|
|
#define CFG_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \
|
|
BR_PS_8 | \
|
|
BR_MS_UPMB | \
|
|
BR_V \
|
|
)
|
|
|
|
/*
|
|
* CS5* configuration for Mil-Std 1553 databus interface.
|
|
* 33 MHz bus, GPCM, no burst.
|
|
* The 1553 interface uses TA and TEA to terminate bus cycles,
|
|
* but we clear SETA and set the cycle length to a large number so that
|
|
* the cycle will still complete even if there is a configuration
|
|
* error that prevents TA from asserting on FPGA accesss.
|
|
*/
|
|
#define CFG_OR5_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
|
|
OR_SCY_15_CLK | \
|
|
OR_EHTR | \
|
|
OR_TRLX | \
|
|
OR_CSNT_SAM | \
|
|
OR_BI \
|
|
)
|
|
|
|
#define CFG_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \
|
|
BR_PS_16 | \
|
|
BR_MS_GPCM | \
|
|
BR_V \
|
|
)
|
|
|
|
/*
|
|
* Boot Flags
|
|
*/
|
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
|
|
|
/*
|
|
* Disk On Chip (millenium) configuration
|
|
*/
|
|
#if !defined(CONFIG_SC)
|
|
#define CFG_MAX_DOC_DEVICE 1
|
|
#undef CFG_DOC_SUPPORT_2000
|
|
#define CFG_DOC_SUPPORT_MILLENNIUM
|
|
#undef CFG_DOC_PASSIVE_PROBE
|
|
#endif
|
|
|
|
/*
|
|
* FEC interrupt assignment
|
|
*/
|
|
#define FEC_INTERRUPT SIU_LEVEL1
|
|
|
|
/*
|
|
* Sanity checks
|
|
*/
|
|
#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
|
|
#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
|
|
#endif
|
|
|
|
#endif /* __CONFIG_GEN860T_H */
|
|
|
|
/* vim: set ts=4 tw=78 ai shiftwidth=4: */
|