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Wolfgang Denk 46263f2de4 SPDX-License-Identifier: convert PIBS licensed files 
This commit adapts the files that were derived from PIBS (PowerPC
Initialization and Boot Software) codeto using SPDX License
Identifiers.

So far, SPDX has not assigned an official License ID for the PIBS
license yet, so this should be considered preliminary.

Note that the following files contained incorrect license information:

	arch/powerpc/cpu/ppc4xx/4xx_uart.c
	arch/powerpc/cpu/ppc4xx/start.S
	arch/powerpc/include/asm/ppc440.h

These files included, in addition to the GPL-2.0 / ibm-pibs dual
license as inherited from PIBS, a GPL-2.0+ license header which was
obviously incorrect.  This has been removed.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>

Conflicts:
	Licenses/README
Acked-by: Stefan Roese <sr@denx.de>
2013-08-19 15:34:14 -04:00
..
flash.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
host_bridge.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
init.S SPDX-License-Identifier: convert PIBS licensed files 2013-08-19 15:34:14 -04:00
jse.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
jse_priv.h Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
Makefile Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
README.txt * Patch by Stephen Williams, 01 Apr 2004: 2004-04-15 23:14:49 +00:00
sdram.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00

README.txt 

JSE Configuration Details

Memory Bank 0 -- Flash chip
---------------------------

0xfff00000 - 0xffffffff

The flash chip is really only 512Kbytes, but the high address bit of
the 1Meg region is ignored, so the flash is replicated through the
region. Thus, this is consistent with a flash base address 0xfff80000.

The placement at the end is to be consistent with reset behavior,
where the processor itself initially uses this bus to load the branch
vector and start running.

On-Chip Memory
--------------

0xf4000000 - 0xf4000fff

The 405GPr includes a 4K on-chip memory that can be placed however
software chooses. I choose to place the memory at this address, to
keep it out of the cachable areas.


Memory Bank 1 -- SystemACE Controller
-------------------------------------

0xf0000000 - 0xf00fffff

The SystemACE chip is along on peripheral bank CS#1. We don't need
much space, but 1Meg is the smallest we can configure the chip to
allocate. We need it far away from the flash region, because this
region is set to be non-cached.


Internal Peripherals
--------------------

0xef600300 - 0xef6008ff

These are scattered various peripherals internal to the PPC405GPr
chip.

SDRAM
-----

0x00000000 - 0x07ffffff  (128 MBytes)