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b36756c769
To align with ARM trusted firmware's change, adjust DRAM timing save area to new position 0x20055000. So we can release the space since 0x2006c000 for the NOBITS region of ARM trusted firmware Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
18 lines
431 B
Text
18 lines
431 B
Text
menu "i.MX8ULP DDR controllers"
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depends on ARCH_IMX8ULP
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config IMX8ULP_DRAM
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bool "imx8m dram"
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config IMX8ULP_DRAM_PHY_PLL_BYPASS
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bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK "
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depends on IMX8ULP_DRAM
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config SAVED_DRAM_TIMING_BASE
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hex "Define the base address for saved dram timing"
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help
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The DRAM config timing data need to be saved into sram
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for low power use.
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default 0x20055000
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endmenu
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