mirror of
https://github.com/AsahiLinux/u-boot
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65cc0e2a65
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
246 lines
6.6 KiB
C
246 lines
6.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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* Author: Hongbo Zhang <hongbo.zhang@nxp.com>
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* This file implements LS102X platform PSCI SYSTEM-SUSPEND function
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*/
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#include <config.h>
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#include <cpu_func.h>
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#include <asm/io.h>
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#include <asm/psci.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <fsl_immap.h>
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#include "fsl_epu.h"
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#define __secure __section("._secure.text")
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#define CCSR_GICD_CTLR 0x1000
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#define CCSR_GICC_CTLR 0x2000
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#define DCSR_RCPM_CG1CR0 0x31c
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#define DCSR_RCPM_CSTTACR0 0xb00
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#define DCFG_CRSTSR_WDRFR 0x8
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#define DDR_RESV_LEN 128
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#ifdef CONFIG_LS1_DEEP_SLEEP
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/*
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* DDR controller initialization training breaks the first 128 bytes of DDR,
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* save them so that the bootloader can restore them while resuming.
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*/
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static void __secure ls1_save_ddr_head(void)
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{
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const char *src = (const char *)CFG_SYS_SDRAM_BASE;
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char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
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struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
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int i;
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out_le32(&scfg->sparecr[2], dest);
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for (i = 0; i < DDR_RESV_LEN; i++)
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*dest++ = *src++;
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}
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static void __secure ls1_fsm_setup(void)
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{
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void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
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void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
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out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
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out_be32(dcsr_rcpm_base + DCSR_RCPM_CG1CR0, 0x00000001);
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fsl_epu_setup((void *)dcsr_epu_base);
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/* Pull MCKE signal low before enabling deep sleep signal in FPGA */
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out_be32(dcsr_epu_base + EPECR0, 0x5);
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out_be32(dcsr_epu_base + EPSMCR15, 0x76300000);
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}
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static void __secure ls1_deepsleep_irq_cfg(void)
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{
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struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
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struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
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u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
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/* Mask interrupts from GIC */
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out_be32(&rcpm->nfiqoutr, 0x0ffffffff);
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out_be32(&rcpm->nirqoutr, 0x0ffffffff);
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/* Mask deep sleep wake-up interrupts while entering deep sleep */
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out_be32(&rcpm->dsimskr, 0x0ffffffff);
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ippdexpcr0 = in_be32(&rcpm->ippdexpcr0);
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/*
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* Workaround of errata A-008646
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* Errata states that read to register ippdexpcr1 always returns
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* zero irrespective of what value is written into it. So its value
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* is first saved to a spare register and then read from it
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*/
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ippdexpcr1 = in_be32(&scfg->sparecr[7]);
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/*
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* To allow OCRAM to be used as wakeup source in deep sleep,
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* do not power it down.
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*/
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out_be32(&rcpm->ippdexpcr1, ippdexpcr1 | RCPM_IPPDEXPCR1_OCRAM1);
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if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC)
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pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 |
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SCFG_PMCINTECR_ETSECRXG1 |
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SCFG_PMCINTECR_ETSECERRG0 |
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SCFG_PMCINTECR_ETSECERRG1;
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if (ippdexpcr0 & RCPM_IPPDEXPCR0_GPIO)
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pmcintecr |= SCFG_PMCINTECR_GPIO;
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if (ippdexpcr1 & RCPM_IPPDEXPCR1_LPUART)
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pmcintecr |= SCFG_PMCINTECR_LPUART;
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if (ippdexpcr1 & RCPM_IPPDEXPCR1_FLEXTIMER)
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pmcintecr |= SCFG_PMCINTECR_FTM;
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/* Always set external IRQ pins as wakeup source */
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pmcintecr |= SCFG_PMCINTECR_IRQ0 | SCFG_PMCINTECR_IRQ1;
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out_be32(&scfg->pmcintlecr, 0);
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/* Clear PMC interrupt status */
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out_be32(&scfg->pmcintsr, 0xffffffff);
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/* Enable wakeup interrupt during deep sleep */
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out_be32(&scfg->pmcintecr, pmcintecr);
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}
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static void __secure ls1_delay(unsigned int loop)
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{
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while (loop--) {
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int i = 1000;
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while (i--)
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;
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}
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}
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static void __secure ls1_start_fsm(void)
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{
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void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
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void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
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struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
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struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
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/* Set HRSTCR */
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setbits_be32(&scfg->hrstcr, 0x80000000);
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/* Place DDR controller in self refresh mode */
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setbits_be32(&ddr->sdram_cfg_2, 0x80000000);
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ls1_delay(2000);
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/* Set EVT4_B to lock the signal MCKE down */
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out_be32(dcsr_epu_base + EPECR0, 0x0);
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ls1_delay(2000);
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out_be32(ccsr_gic_base + CCSR_GICD_CTLR, 0x0);
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out_be32(ccsr_gic_base + CCSR_GICC_CTLR, 0x0);
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/* Enable all EPU Counters */
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setbits_be32(dcsr_epu_base + EPGCR, 0x80000000);
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/* Enable SCU15 */
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setbits_be32(dcsr_epu_base + EPECR15, 0x90000004);
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/* Enter WFI mode, and EPU FSM will start */
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__asm__ __volatile__ ("wfi" : : : "memory");
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/* NEVER ENTER HERE */
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while (1)
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;
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}
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static void __secure ls1_deep_sleep(u32 entry_point)
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{
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struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
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struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
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struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
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#ifdef QIXIS_BASE
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u32 tmp;
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void *qixis_base = (void *)QIXIS_BASE;
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#endif
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/* Enable cluster to enter the PCL10 state */
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out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
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/* Save the first 128 bytes of DDR data */
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ls1_save_ddr_head();
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/* Save the kernel resume entry */
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out_le32(&scfg->sparecr[3], entry_point);
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/* Request to put cluster 0 in PCL10 state */
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setbits_be32(&rcpm->clpcl10setr, RCPM_CLPCL10SETR_C0);
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/* Setup the registers of the EPU FSM for deep sleep */
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ls1_fsm_setup();
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#ifdef QIXIS_BASE
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/* Connect the EVENT button to IRQ in FPGA */
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tmp = in_8(qixis_base + QIXIS_CTL_SYS);
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tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
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tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
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out_8(qixis_base + QIXIS_CTL_SYS, tmp);
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/* Enable deep sleep signals in FPGA */
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tmp = in_8(qixis_base + QIXIS_PWR_CTL2);
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tmp |= QIXIS_PWR_CTL2_PCTL;
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out_8(qixis_base + QIXIS_PWR_CTL2, tmp);
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/* Pull down PCIe RST# */
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tmp = in_8(qixis_base + QIXIS_RST_FORCE_3);
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tmp |= QIXIS_RST_FORCE_3_PCIESLOT1;
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out_8(qixis_base + QIXIS_RST_FORCE_3, tmp);
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#endif
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/* Enable Warm Device Reset */
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setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN);
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setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR);
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/* Disable QE */
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setbits_be32(&gur->devdisr, CCSR_DEVDISR1_QE);
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ls1_deepsleep_irq_cfg();
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psci_v7_flush_dcache_all();
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ls1_start_fsm();
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}
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#else
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static void __secure ls1_sleep(void)
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{
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struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
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struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
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#ifdef QIXIS_BASE
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u32 tmp;
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void *qixis_base = (void *)QIXIS_BASE;
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/* Connect the EVENT button to IRQ in FPGA */
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tmp = in_8(qixis_base + QIXIS_CTL_SYS);
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tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
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tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
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out_8(qixis_base + QIXIS_CTL_SYS, tmp);
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#endif
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/* Enable cluster to enter the PCL10 state */
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out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
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setbits_be32(&rcpm->powmgtcsr, RCPM_POWMGTCSR_LPM20_REQ);
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__asm__ __volatile__ ("wfi" : : : "memory");
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}
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#endif
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void __secure ls1_system_suspend(u32 fn, u32 entry_point, u32 context_id)
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{
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#ifdef CONFIG_LS1_DEEP_SLEEP
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ls1_deep_sleep(entry_point);
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#else
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ls1_sleep();
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#endif
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}
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