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cb2ddb291e
In case when ARM Trusted Firmware changes the default address of PCIe regions (which can be done for devices with 4 GB RAM to maximize the amount of RAM the device can use) we add code that looks at how ATF changed the PCIe windows in the CPU Address Decoder and changes given device-tree blob accordingly. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
339 lines
7.6 KiB
C
339 lines
7.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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* Copyright (C) 2020 Marek Behun <marek.behun@nic.cz>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <linux/libfdt.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/armv8/mmu.h>
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#include <sort.h>
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/* Armada 3700 */
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#define MVEBU_GPIO_NB_REG_BASE (MVEBU_REGISTER(0x13800))
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#define MVEBU_TEST_PIN_LATCH_N (MVEBU_GPIO_NB_REG_BASE + 0x8)
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#define MVEBU_XTAL_MODE_MASK BIT(9)
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#define MVEBU_XTAL_MODE_OFFS 9
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#define MVEBU_XTAL_CLOCK_25MHZ 0x0
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#define MVEBU_XTAL_CLOCK_40MHZ 0x1
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#define MVEBU_NB_WARM_RST_REG (MVEBU_GPIO_NB_REG_BASE + 0x40)
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#define MVEBU_NB_WARM_RST_MAGIC_NUM 0x1d1e
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/* Armada 3700 CPU Address Decoder registers */
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#define MVEBU_CPU_DEC_WIN_REG_BASE (size_t)(MVEBU_REGISTER(0xcf00))
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#define MVEBU_CPU_DEC_WIN_CTRL(w) \
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(MVEBU_CPU_DEC_WIN_REG_BASE + ((w) << 4))
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#define MVEBU_CPU_DEC_WIN_CTRL_EN BIT(0)
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#define MVEBU_CPU_DEC_WIN_CTRL_TGT_MASK 0xf
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#define MVEBU_CPU_DEC_WIN_CTRL_TGT_OFFS 4
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#define MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM 0
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#define MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE 2
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#define MVEBU_CPU_DEC_WIN_SIZE(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0x4)
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#define MVEBU_CPU_DEC_WIN_BASE(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0x8)
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#define MVEBU_CPU_DEC_WIN_REMAP(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0xc)
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#define MVEBU_CPU_DEC_WIN_GRANULARITY 16
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#define MVEBU_CPU_DEC_WINS 5
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#define MAX_MEM_MAP_REGIONS (MVEBU_CPU_DEC_WINS + 2)
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#define A3700_PTE_BLOCK_NORMAL \
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(PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE)
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#define A3700_PTE_BLOCK_DEVICE \
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(PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE)
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#define PCIE_PATH "/soc/pcie@d0070000"
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DECLARE_GLOBAL_DATA_PTR;
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static struct mm_region mvebu_mem_map[MAX_MEM_MAP_REGIONS] = {
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{
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/*
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* SRAM, MMIO regions
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* Don't remove this, a3700_build_mem_map needs it.
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*/
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.phys = SOC_REGS_PHY_BASE,
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.virt = SOC_REGS_PHY_BASE,
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.size = 0x02000000UL, /* 32MiB internal registers */
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.attrs = A3700_PTE_BLOCK_DEVICE
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},
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};
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struct mm_region *mem_map = mvebu_mem_map;
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static int get_cpu_dec_win(int win, u32 *tgt, u32 *base, u32 *size)
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{
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u32 reg;
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reg = readl(MVEBU_CPU_DEC_WIN_CTRL(win));
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if (!(reg & MVEBU_CPU_DEC_WIN_CTRL_EN))
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return -1;
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if (tgt) {
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reg >>= MVEBU_CPU_DEC_WIN_CTRL_TGT_OFFS;
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reg &= MVEBU_CPU_DEC_WIN_CTRL_TGT_MASK;
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*tgt = reg;
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}
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if (base) {
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reg = readl(MVEBU_CPU_DEC_WIN_BASE(win));
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*base = reg << MVEBU_CPU_DEC_WIN_GRANULARITY;
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}
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if (size) {
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/*
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* Window size is encoded as the number of 1s from LSB to MSB,
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* followed by 0s. The number of 1s specifies the size in 64 KiB
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* granularity.
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*/
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reg = readl(MVEBU_CPU_DEC_WIN_SIZE(win));
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*size = ((reg + 1) << MVEBU_CPU_DEC_WIN_GRANULARITY);
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}
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return 0;
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}
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/*
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* Builds mem_map according to CPU Address Decoder settings, which were set by
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* the TIMH image on the Cortex-M3 secure processor, or by ARM Trusted Firmware
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*/
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static void build_mem_map(void)
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{
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int win, region;
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region = 1;
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for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
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u32 base, tgt, size;
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u64 attrs;
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/* skip disabled windows */
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if (get_cpu_dec_win(win, &tgt, &base, &size))
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continue;
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if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM)
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attrs = A3700_PTE_BLOCK_NORMAL;
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else if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE)
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attrs = A3700_PTE_BLOCK_DEVICE;
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else
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/* skip windows with other targets */
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continue;
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mvebu_mem_map[region].phys = base;
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mvebu_mem_map[region].virt = base;
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mvebu_mem_map[region].size = size;
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mvebu_mem_map[region].attrs = attrs;
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++region;
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}
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/* add list terminator */
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mvebu_mem_map[region].size = 0;
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mvebu_mem_map[region].attrs = 0;
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}
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void enable_caches(void)
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{
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build_mem_map();
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icache_enable();
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dcache_enable();
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}
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int a3700_dram_init(void)
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{
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int win;
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gd->ram_size = 0;
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for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
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u32 base, tgt, size;
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/* skip disabled windows */
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if (get_cpu_dec_win(win, &tgt, &base, &size))
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continue;
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/* skip non-DRAM windows */
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if (tgt != MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM)
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continue;
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/*
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* It is possible that one image was built for boards with
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* different RAM sizes, for example 512 MiB and 1 GiB.
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* We therefore try to determine the actual RAM size in the
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* window with get_ram_size.
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*/
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gd->ram_size += get_ram_size((void *)(size_t)base, size);
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}
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return 0;
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}
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struct a3700_dram_window {
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size_t base, size;
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};
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static int dram_win_cmp(const void *a, const void *b)
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{
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size_t ab, bb;
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ab = ((const struct a3700_dram_window *)a)->base;
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bb = ((const struct a3700_dram_window *)b)->base;
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if (ab < bb)
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return -1;
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else if (ab > bb)
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return 1;
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else
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return 0;
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}
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int a3700_dram_init_banksize(void)
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{
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struct a3700_dram_window dram_wins[MVEBU_CPU_DEC_WINS];
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int bank, win, ndram_wins;
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u32 last_end;
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size_t size;
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ndram_wins = 0;
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for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
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u32 base, tgt, size;
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/* skip disabled windows */
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if (get_cpu_dec_win(win, &tgt, &base, &size))
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continue;
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/* skip non-DRAM windows */
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if (tgt != MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM)
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continue;
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dram_wins[win].base = base;
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dram_wins[win].size = size;
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++ndram_wins;
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}
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qsort(dram_wins, ndram_wins, sizeof(dram_wins[0]), dram_win_cmp);
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bank = 0;
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last_end = -1;
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for (win = 0; win < ndram_wins; ++win) {
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/* again determining actual RAM size as in a3700_dram_init */
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size = get_ram_size((void *)dram_wins[win].base,
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dram_wins[win].size);
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/*
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* Check if previous window ends as the current starts. If yes,
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* merge these windows into one "bank". This is possible by this
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* simple check thanks to mem_map regions being qsorted in
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* build_mem_map.
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*/
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if (last_end == dram_wins[win].base) {
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gd->bd->bi_dram[bank - 1].size += size;
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last_end += size;
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} else {
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if (bank == CONFIG_NR_DRAM_BANKS) {
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printf("Need more CONFIG_NR_DRAM_BANKS\n");
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return -ENOBUFS;
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}
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gd->bd->bi_dram[bank].start = dram_wins[win].base;
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gd->bd->bi_dram[bank].size = size;
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last_end = dram_wins[win].base + size;
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++bank;
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}
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}
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/*
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* If there is more place for DRAM BANKS definitions than needed, fill
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* the rest with zeros.
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*/
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for (; bank < CONFIG_NR_DRAM_BANKS; ++bank) {
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gd->bd->bi_dram[bank].start = 0;
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gd->bd->bi_dram[bank].size = 0;
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}
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return 0;
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}
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static u32 find_pcie_window_base(void)
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{
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int win;
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for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
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u32 base, tgt;
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/* skip disabled windows */
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if (get_cpu_dec_win(win, &tgt, &base, NULL))
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continue;
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if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE)
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return base;
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}
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return -1;
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}
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int a3700_fdt_fix_pcie_regions(void *blob)
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{
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u32 new_ranges[14], base;
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const u32 *ranges;
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int node, len;
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node = fdt_path_offset(blob, PCIE_PATH);
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if (node < 0)
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return node;
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ranges = fdt_getprop(blob, node, "ranges", &len);
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if (!ranges)
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return -ENOENT;
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if (len != sizeof(new_ranges))
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return -EINVAL;
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memcpy(new_ranges, ranges, len);
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base = find_pcie_window_base();
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if (base == -1)
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return -ENOENT;
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new_ranges[2] = cpu_to_fdt32(base);
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new_ranges[4] = new_ranges[2];
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new_ranges[9] = cpu_to_fdt32(base + 0x1000000);
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new_ranges[11] = new_ranges[9];
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return fdt_setprop_inplace(blob, node, "ranges", new_ranges, len);
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}
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void reset_cpu(ulong ignored)
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{
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/*
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* Write magic number of 0x1d1e to North Bridge Warm Reset register
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* to trigger warm reset
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*/
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writel(MVEBU_NB_WARM_RST_MAGIC_NUM, MVEBU_NB_WARM_RST_REG);
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}
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/*
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* get_ref_clk
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*
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* return: reference clock in MHz (25 or 40)
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*/
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u32 get_ref_clk(void)
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{
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u32 regval;
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regval = (readl(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
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MVEBU_XTAL_MODE_OFFS;
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if (regval == MVEBU_XTAL_CLOCK_25MHZ)
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return 25;
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else
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return 40;
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}
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